Transcript ELEN 468 Advanced Logic Design

ELEN 468
Advanced Logic Design
Lecture 13
Synthesis of Combinational Logic II
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Verilog Code Styles
One behavior or functionality can be
described with Verilog in different styles
Different styled Verilog code may
generate different synthesis results
Need to understand such difference to
design circuit efficiently
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General Rules for Combinational Logic
Avoid to model specific technology
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Synthesis functionality
Ignore timing
Avoid feedback loops

Feedback loop may result in sequential
circuit
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Combinational Synthesis from Netlist
of Primitives
Let design be synthesized to remove
any redundant logic
y = (a+b)•(b+c)
y = a•c + b
Example 8.6, page 300
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Combinational Synthesis from UDPs
Any combinational UDP can be
synthesized
Table entry with “x” is ignored
“?” is treated as don’t care
Post-synthesis simulation result may be
different from pre-synthesis simulation
if a table has “x” or “?”
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Combinational Synthesis from a
Cyclic Behavior
Combinational logic can be described by
a cyclic behavior – enumerate all input
cases, otherwise a latch will be inferred
A register variable does not necessarily
implies storage element
Signals appear at RHS of assignment
cannot appear on LHS
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Combinational Synthesis from a
Cyclic Behavior: Example
module and4_behav( y, x );
input [3:0] x;
output y;
reg y;
integer k;
always @ ( x )
begin: check
y = 1;
for ( k = 0; k <= 3; k = k+1 )
if ( x[k] == 0 )
begin
y = 0;
disable check;
end
end
endmodule
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y
x
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Combinational Synthesis from
Function or Task
Functions inherently represent
combinational logic
Avoid incomplete case statements or
incomplete conditionals
Task has similar restrictions as a
function

Avoid timing controls in tasks
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Construct to Avoid in
Combinational Synthesis
Multiple event controls in same procedural block
Named event with edge-sensitive event control
Feedback loops
PCA with event or delay control
Parallel threads: fork … join
Suspended activity: wait
External disable statement
Procedural loops with timing controls
Data-dependent loops
Tasks with timing controls
Sequential UDPs
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Simulation Efficiency and PCA
module orNand1(y, en, a, b, c, d );
input en, a, b, c, d;
output y;
reg y;
always @ (en or a or b or c or d )
y = ~( en & (a | b) & (c | d) );
endmodule
Less efficient
module orNand1(y, en, a, b, c, d );
input en, a, b, c, d;
output y;
reg y;
always @ ( en )
if ( en )
assign y = ~((a|b) & (c|d));
else
assign y = 1;
endmodule
Generally, PCA is efficient on implementing combinational logic
in behavioral descriptions
Keyword deassign is only used in sequential circuits.
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Note
Synthesis tool may issue a confusing
message about syntax violations
because it does not accept your coding
style, even though your code is correct
in syntax
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Unexpected and Unwanted Latch
Combinational logic must specify output
value for all input values
Incomplete case statements and
conditionals (if) imply
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Output should retain value for unspecified
input values
Unwanted latches
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Example of Unwanted Latch
module myMux( y, selA, selB, a, b );
input selA, selB, a, b;
output y;
reg y;
always @ ( selA or selB or a or b )
case ( {selA, selB} )
2’b10: y = a;
2’b01: y = b;
endcase
endmodule
b
selA’
selB
selA
selB’
en
y
latch
a
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Synthesis of case and if
case and if statement imply priority
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Synthesis tool will determine if case items of a
case statement are mutually exclusive
If so, synthesis will treat them with same priority
and synthesize a mux
A synthesis tool will treat casex and casez
same as case
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“x” and “z” will be treated as don’t cares
Post-synthesis simulation result may be different
from pre-synthesis simulation
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Example of if and case
…
input [3:0] data;
output [1:0] code;
reg [1:0] code;
always @(data)
begin // implicit priority
if ( data[3] ) code = 3;
else if (data[2]) code = 2;
else if (data[1]) code = 1;
else if (data[0]) code = 0;
else code = 2’bx;
end
…
…
input [3:0] data;
output [1:0] code;
reg [1:0] code;
always @(data)
case (data)
4’b1000: code = 3;
4’b0100: code = 2;
4’b0010: code = 1;
4’b0001: code = 0;
default: code = 2’bx;
endcase
…
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Technology Mapping
Map logic gates to library cells
Synthesis tool may map y = a + b into
a library adder
Synthesis tool will not recognize an
adder that is implicitly represented by a
hierarchical netlists
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Buses
module stuffToBus1( data, enable, clock );
input enable, clock;
output [31:0] data;
reg [31:0] outToBus;
assign data = ( enable ) ? outToBus : 32’bz;
// code to generate outToBus
// …
endmodule
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Bi-directional Bus Drivers
module stuffToBus2 ( data, clock, send_data, rcv_data );
input clock, send_data, rcv_data;
inout [31:0] data_to_from_bus;
reg [31:0] reg_to_bus;
wire [31:0] dataToFrom_bus, inbound_data;
assign inbound_data = (rcv_data) ? dataToFrom_bus : 32’bz;
assign dataToFrom_bus = (send_data) ? Reg_to_bus : dataToFrom_bus;
endmodule
rcv_data
inbound_data
Core Circuit
32
32
32
reg_to_bus
dataToFrom_bus
send_data
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Exercise 4
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Simulation Output
`timescale 1ns/100ps
module m(y,x);
output y, input x;
not #1.234 (y,x);
endmodule
`timescale 10ns/100ps
module modA;
wire a; reg b;
m m1(b, a);
initial
$monitor ( $time,
“ realtime=%f, a=%b, b=%b”,
$readtime, a, b);
initial begin
#10 a = 0; #10 a = 1; #10 $finish;
end
endmodule
ELEN 468 Lecture 13
0 realtime=0.0 a=x b=x
10 realtime=10.0 a=0 b=x
10 realtime=10.12 a=0 b=1
20 realtime=20.0 a=1 b=1
20 realtime=20.12 a=1 b=0
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Draw Waveform
module wave();
reg a, b, c;
initial begin
#1 a = 1;
c <= #2 a;
b <= #1 c;
#1 a = 0;
b <= 0;
fork
#1 a = 1;
#2 b = 0;
c = a;
join
a <= 0;
end
endmodule
a
1
2
3
4
1
2
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4
1
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b
c
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Transistor Level Structural Code
module nand2( y, a, b );
output y;
input a, b;
supply1 pwr;
Vdd
A
B
Y
pulldown ( y );
pmos( y, pwr, a );
pmos( y, pwr, b );
endmodule
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