Transcript CMOS RFIC Design - Hong Kong University of Science and

CMOS RFIC Design for
Direct Conversion
Receivers
Zhaofeng ZHANG
Outline of Presentation
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Background Introduction
Design Issues and Solutions
A Direct Conversion Pager Receiver
Conclusion
Research Goal
• Low Cost
– Process: CMOS
• Device is good enough
• Improved passive components
– Integration level
• Minimize external components
• Minimize IC area and pin numbers
• Low Power
– High integration = low power
– Low power individual block design
– System architecture is important
Heterodyne Receivers
• High IF: more than 2 down-conversions
– Best sensitivity
– Need off-chip image-rejection SAW filters and
channel-selection filters
– Highest cost, high power, low integration
• Low IF
– Relaxed image-rejection requirement compared
to high-IF
– No DC offset problem
– Quadrature LO is required
– Flicker noise may be a problem
– High integration level, low cost
Homodyne Receivers
I
LNA
90º
Q
Pros
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Simple architecture
No image problem
No 50ohm interfaces
High integration level
Lowest cost, low power
Cons
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DC offsets
Flicker noise
LO leakage
Even-order distortion
Origin of Problem
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DC offsets
Flicker noise
LO leakage
Even-order distortion
Linearity requirement
Noise requirement
IQ mismatch
All problems are limited by the mixer design!
The mixer: the most critical component!
Our research focus!
DC Offsets & LO
Leakage
LO Leakage
Zero IF + Offset
• The offset originates from self-mixing.
• It can be as large as mV range at the mixer output.
• It varies with the environment and moving speed of
the mobile and changes with time.
• The maximum bandwidth can be as large as kHz range.
• LO leakage forms an interference to other receivers.
DC offset
Frequency
Flicker noise
Frequency
Broad Band
High-pass corner
Frequency
Signal
Frequency
Offset-Free
Narrow Band
DC Offsets
Spectrum Illustration
Existing Solutions on DC
Offset
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AC coupling or high pass filtering
Autozeroing or double sampling
Offset cancellation in digital domain
Double LO frequency method [ISSCC99]
Adaptive dual-loop algorithm combined with the mixer
[RAWCON00]
• Pulse-width-modulation based bipolar harmonic mixer [CICC97]
However, these methods are either not so
effective or too complicated, or not suitable
for CMOS process.
BB Signal
LO Leakage
DC Offset
frf
flo=frf
RF Signal
0
BB Signal
LO Leakage
flo=frf/2
frf
2flo=frf
0
flo
Our Work
RF Signal
Conventional
Proposed Harmonic Mixing
Square-law Based Mixer
RF
3V
Voltage
IF
No
Coupling
Current
2
Vrf+
Vrf-
Voltage
LO
Vlo+
• LO leakage free.
• Ideally self-mixing free.
• Current controlled switching.
• No noise contribution from LO stage.
Vlo-
Flicker Noise Reduction
3V
I0
Vrf+
Vlo+
Vrf-
Vlo-
• Flicker noise is proportional to the current.
• Current injection is used to reduce flicker noise.
• No noise contribution from current source too.
Offset Cancellation
20
TSMC0.35
Gain (dB)
10
0
>35dB
-10
-20
-30
-40
-22
-20
-18
-16
LO Input Power (dBm)
Noise Figure @ 10kHz (dB)
Noise Performance
60
50
40
30
20
400
600
800
1000
Injected Current I0 (A)
How to improve more?
• However, flicker noise is still too large due to CMOS
devices, minimum noise figure achieved is larger
than 24dB @ 10kHz for CMOS harmonic mixer. It
requires a high gain and low noise LNA to overcome
flicker noise while the front-end linearity suffers.
• For a narrow-band communication system such as
FLEX pager, the noise requirement at low frequency
is very tough.
• It is well known that bipolar device is a good
candidate to eliminate flicker noise.
• But, can we do it in a CMOS process and how good
is the device? YES!
Lateral Bipolar Transistor
in a Bulk CMOS Process
W.T. Holman95
Base
Emitter
Gate
Gate
P+
Emitter
Vertical
Collector
N+
Base
Collector
Ground
Lateral
Collector
Physical Model of LBJT
Gate
Collector
Base Q3
P-Sub
M1
Q1
D. Mac98
Emitter
Q2
Base
P-Sub
Pure LBJT: M1, Q3 off, Q1, Q2 on.
Gummel Plot of LBJT
TSMC0.35
>40 at mAs
max fT 4GHz
LBJT Harmonic Mixer
VDD
VLO+
M1
Q1
VRF+
OUTRL
VLO-
M2
Ii
Q2
VRFOUT+
RL
Noise Performance
Large LO improves noise.
Even Order Distortion
RF Signal
a1x+a2x2+a3x3+…
BB Signal
Interference
f1 f2
frf
IM2 (f2-f1)
0
• It is mainly introduced by layout asymmetry and device mismatch.
• Since direct-conversion, the intermodulation components IM2 will
fall into the demodulated signal spectrum.
• Therefore, good IIP2 is required for homodyne receivers.
• It is found that varying the loading resister or voltage bias can
compensate the device mismatch and improve IIP2 significantly.
IIP2 Improvement
Same DC bias
Compensation
IIP2=18dBm
IIP2>40dBm
LBJT Mixer Performance
Technology
TSMC 3M2P 0.35m
VDD
Signal Gain
3V
+15dB
DC offset suppression
Noise figure @ 10kHz
1dB compression point
Input-referred IP3
>30dB
<18dB
>-20dBm
>-9dBm
Input-referred IP2
Power consumption
>+40dBm
<2.2mW
Summary on Mixer
• Flicker noise free, corner frequency is
below 10kHz.
• DC offset free, more than 30dB DC offset
suppression is achieved.
• No LO leakage problem.
• Sufficient IIP2 after bias compensation.
• High gain and low power consumption.
• Complete CMOS process.
• Suitable for CMOS direct conversion
applications.
Difficulties in FLEX Pager
BER @ 12dB Eb/N0
0
-20
0
5
10
kHz
Big Challenges
• Narrow band modulation
• Significant energy near DC
• High pass filtering is not viable
• DC offset problem
• Flicker noise is significant
10 -2
High pass corner (Hz)
10 0
DC Offset Effect
-10 -5
10 -1
BER
dB
-1
-40
-60
High pass effect
FLEX 6400, 4FSK
10 -2
4
8
12
Eb/N0 (dB)
16
4-FSK Pager Receiver
AGC
RF: Zhaofeng
LNA
45
VCO
BB: Zhiheng
DEMOD
AGC
• Fully differential architecture to reject substrate noise.
• Harmonic mixers are used to solve time-varying DC offset.
• Peak detectors are used to cancel static DC offset.
• High front-end gain and current injection to reduce flicker noise.
LNA
• Non-quasi-static
phenomenon makes
it unnecessary to do
on-chip matching.
• Off-chip matching by
a single inductor and
a balun.
• |S11|<-20dB @
930MHz
• Both on-chip and offchip inductive loads
were tried.
Double Balanced Mixer
Improve the linearity; Provide constant impedance to LNA;
Current injection provides more than 20dB flicker noise reduction.
Ring Oscillator
Half RF frequency,
Provide 45 phase.
Static DC Offset Cancellation
Zero-IF
4-FSK
Signal
Peak
Detector
Fmin200Hz
Performance Summary
Front-End
Off-chip ind On-chip ind
Pager receiver with off-chip ind
RF/BB gain:
51.13dB
40.33dB
Maximum Gain:
NF@10kHz:
11.5dB
24.0dB
Noise figure@10kHz: 14.5dB
NF@100kHz:
5.8dB
15.0dB
Overall DC offset at LPF output: <1mV
IIP3:
-26dBm
-20.7dBm
IIP2:
-10dBm
-5.6dBm
(Signal: 400mV)
Operating frequency: 930.1MHz
LO frequency:
465MHz
IQ gain mismatch:
< 0.3dB
IQ phase mismatch:
< 5
RF/BB over LO/BB: > 54dB
Self-mixing free
Input matching:
< -20dB
Power dissipation:
52.76mW
62dB
Power dissipation:
58mW
Technology:
TSMC0.35m 4M2P
Die area:
Baseband (Zhiheng)
AGC gain:
LPF:
4.6 mm2
-14.5dB~18.6dB
Pass-band gain-6.2dB, ripple 0.5dB (9kHz)
Stop-band attenuation  63dB ( 17.8kHz)
Offset cancellation:
<2mV (under ±100mV input offset)
Input Referred Noise:
600nV/ Hz @ 10kHz
Clock Recovery:
Capture range > 550Hz
Power dissipation:
5.4mW (including all testing buffers)
Die Photo
AGC
LNA
DEMOD
45
VCO
AGC
RF Front-End
Mixer
Mixer
AGC
LPF
Base Band Circuitry[Zhiheng]
RF Front-End
Summary on Pager
Receiver
• Feasibility of direct conversion has been
demonstrated.
• Proposed harmonic mixing technique solves selfmixing induced DC offset problem successfully.
• With the help of static DC offset cancellation, the total
DC offset is less than 1mV at the receiver output.
• The modified ZIFZCD 4-FSK demodulator functions
correctly.
• A 4-FSK FLEX pager receiver in a single chip has
been implemented successfully.
Conclusion
• Circuit design for direct-conversion has been
discussed.
– DC offset: more than 30dB improvement
– LO leakage: no longer a problem
– Flicker noise: corner frequency is less than kHz
due to lateral bipolar device.
– IIP2: larger than +40dBm after bias compensation.
• System on chip has been successfully
demonstrated using CMOS direct conversion
architecture.