Transcript MODERN presentation template

LETI MODERN Contribution to WP5
• Contribution to WP5.2: Demonstrator : design,
implementation and characterization
• Status :
–
–
–
–
Design of a full chip in 32 nm : LoCoMoTIV
Full AVFS architecture
Including WP3 and WP4 IP contributions
PG tape : December
2008
• Deliverables:
– D5.2.2: Test chip simulation results : on track
– D5.2.3 : IP block design and layout : on track
– D5.5.4 : test chip characterization : on track
© CEA 2006. Tous droits réservés.
Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA
All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
1
A dynamic adaptive Architecture
4
3,5
Puissance (Consommation)
– Performances improvements:
DVFS vs AVFS
Puissance (Série4)
3
200
DVFS
AVFS
180
Puissance (Période min)
2,5
3,4
Puissance (PERIODE MIN MONITORS)
3,2
2
3
160
Decision Maker
Parameter Control
2,8
1,5
140
Same Speed
2,6
1
2,4
Diagnostic
S
120
1,1
1,15
1,2
1,25
2,2
100
80
1,8
60
1,6
1,4
40
1,2
Same Power
1
20
0,9
0,95
1
1,05
1,1
1,15
1,2
K
K : Actuators
S : Sensors
S
Action
K
S
Puissance (Série4)
K
Digital Block
Puissance (Période min)
1 Power/Frequency domain
Puissance (PERIODE MIN MONITORS)
Period (ns)
2
S
Puissance (Consommation)
Circuit
2008
Power (mW)
05
4,5
1,25
Power supply (V)
© CEA 2006. Tous droits réservés.
Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA
All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
2
Architecture Overview
A fine grain Local Dynamic Adaptive voltage and
frequency scaling architecture
• Diagnostic:
– Process-Voltage-Temperature
– Timing fault detection or prevention (WP3)
• Actuators:
– Based on Vdd-hopping
2008
– Local clock generation using FLL
• Power/Variability Control
RunTime
ANOC
CVPU
0.9v
0.7v
CVPU
PE
0.9v
0.7v
PE
– Local control with minimum hardware (WP4)
– Global control : high level algorithms
Main HW objective : a minimum hardware based on standard cells
and simple analog macros for flow insertion and maximum efficiency
© CEA 2006. Tous droits réservés.
Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA
All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
3
LoCoMoTIV architecture
Local Compensation of Modern Technology Induced Variability
An AVFS GALS approach at fine grain to reach an optimum energetic
point according to PVT variations
ITs
Asynchronous NoC
ITs
WDT
DMA
L2-RAM
4 XP70 µP
Dedicated memory
blocks
V/F Local actuators
Timing Fault
Detectors
PVT sensors
Local Controller
CVP : ClockVraiability-Power
M
NI
NI
NI
CVP-U
CVP-U
NI
NI
Memory
Mapped
Peripherals
NI
16KB P-$
16KB P-$
16KB P-$
32-KB TCDM
32-KB TCDM
32-KB TCDM
32-KB TCDM
STxP70-V4
Hopping /
(Rev.
FLL A)
+ ITC
PVT
S
#1
STxP70-V4
Hopping /
(Rev.
FLL A)
+ ITC D-$
PVT
S
#2
STxP70
STxP70
OCE
OCE
OCE
OCE
TMS TCK TDI TDO BI
BO
TMS TCK TDI TDO BI
HWS
M
NI
ANOC
16KB P-$
2008
S
NI
BO
TMS TCK TDI TDO BI
BO
TMS TCK TDI TDO BI
BO
Debug & Test Unit
© CEA 2006. Tous droits réservés.
Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA
All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
4
BACK
LoCoMoTIV flooplan
Fully digital FLL :
Frequency
generation
PVT probes
Hopping transition
and switches :
Voltage genration
PE1
PE0
L2RAM
ANOC
2008
CDMA
PE2
PE3
© CEA 2006. Tous droits réservés.
Toute reproduction totale ou partielle sur quelque support que ce soit ou utilisation du contenu de ce document est interdite sans l’autorisation écrite préalable du CEA
All rights reserved. Any reproduction in whole or in part on any medium or use of the information contained herein is prohibited without the prior written consent of CEA
5
Task 5.2
IFXA  Objective and Outline
Objective: development and verification of monitor & control (M&C)
strategies for AMS&RF circuits to deal with aging/reliability issues and
aging induced parameter variations in nanometer CMOS.
Close link to T3.3 (M&C concept development)
Outline
– Basic aging/reliability assessment  identify sensitivities
• Aging simulations (proof of sim.-concept, model-hardware correlation in T5.2)
• Dedicated test-structures for transient effects and aging-parameter-variations
– Development of M&C concepts  T3.3
– Implementation and verification of M&C concepts
• Silicon based proof of concept
• Concept development for accelerated aging/stress tests  T5.2
• Development of characterization methods (fast transient effects)  T5.2
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 6
Task 5.2
IFXA  Completed and Remaining Activities
Test-chip status:
– TC #1 (32nm CMOS): taped, lab characterization completed
– TC #2 (32nm CMOS): taped, lab characterization on-going
– TC #3 (28nm CMOS): design on-going, tape-out end 2010
Status basic aging/reliability assessment (-> circuit level results)
– Circuit level aging simulation flow proven on TC1 (OpAmps, VCOs)
– Structures for transient effects and aging-variations implemented on TC2
OpAmp: Offset drift
VCO: aging of startup VDD
Static offset
Recovery
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 7
Task 5.2
IFXA  Completed and Remaining Activities
BACK
Status implementation & verification of M&C concepts
– Accelerated aging test-setup proven on TC1 and TC2 (OpAmps, VCOs)
– Fast offset characterization method (transient effects) proven on TC2
– Measurements to be finalized on TC2
•
•
•
•
ADC incl. error correction (static & transient offsets)
Switch degradation monitor circuits
Variations of aging parameters
Novel burn-in concept (to increase robustness and compensate PV)
– Macros to be implemented on TC3
V-Sense
Figure 5: Chip Micrograph
Refbuf
NDEMOS
PDEMOS
ESD
PID
ESD
ESD
ESD
• Switch control circuits to be implemented on TC3
• DCDC test-structures
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 8
Task 3.3
IFXA  Key Results Aging Assessment
Majority of key blocks AMS & RF is inherently robust (“self-regulation”)
Sensitive cases
– Non-linear / asymmetric operation (comparator)
– Full scale driven devices (switches, VCO, …)
Transient effects (recovery) significantly contribute
Variations of aging parameters need to be considered ( T5.2)
Scaling 65nm to 32nm: not absolute values but sensitivities change
OpAmp: Offset drift
VCO: aging of startup VDD
Static offset
Recovery
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 9
Task 3.3
IFXA  Key Results M&C Development
Switches
– Monitor concepts: ring oscillator, current sensing
– Control: “frequency locked loop”, analog control loop
Aging induced offsets
– Avoid offset generation: e.g. chopping (comparator)
– Correction of static & dynamic effects: e.g. error correction by redundancy
– Burn-in: dedicated stress to increase robustness and compensate PV
stress pattern
control voltage
ADC search algorithm incl. redundancy
...
Inv 1
...
Inv 2
Inv n
switch replicas
enable
ref.
switch on-voltage
Phase
Frequency
Detector
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
Charge
Pump
Loop
Filter
Ringo
Monitor
CONFIDENTIAL 10
Frequency
Divider
Task 3.3
IFXA  Completed and Remaining Activities
Testchip #1 and #2 taped, samples not fully characterized, design of #3
on-going
Basic aging/reliability assessment  almost completed
– Simulations completed, sim.-concept verified (TC1, OpAmps, VCOs)
– Structures for transient effects and aging-variations implemented on TC2
Development of M&C concepts  completed
Implementation and verification of M&C concepts  ongoing
– Accelerated aging test-setup proven on TC1 and TC2
– Fast offset characterization method proven on TC2
– TC2
• Switch monitor circuits
• ADC incl. error correction
– TC3
• Switch control circuits to be implemented on TC3
• DCDC test-structures
• Concept development for accelerated aging/stress tests
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 11
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 12
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 13
BACK
MODERN General Meetings
Catania, Nov. 9 & 10, 2010
CONFIDENTIAL 14
MODERN
WP5
THALES foreseen activities
10 November 2010
THL activities in MODERN linked to WP5

Up to now we (THL) have had contributions in WP4 to develop a
SystemC simulator of a predictable fault-tolerant multicore chip (based
on the ISD network) with embedded middleware and operating libraries.







developed a processor tile
designed and implemented fault injection scenarios
design the multicore chip with ISD network
implemented a SystemC simulator of the chip
designed and implemented operating libraries, middleware and tools
modified in-house tools to generate parallel code for this architecture
designed, developed and implemented a video detection algorithm on top of the
architecture based on the Viola & Jones face detection (Haar filters).
20 November 2009
WP4 Web Meeting
Slide 16 of 19
Architecture (SystemC)
iNoC : Internal Network OCP TL2
Supervisor : TILE 0
CTR
CTR
DMA
DMA
NIM
LMEM
TILE 1
ACC
LMEM
CTR
…
NIM
DMA
TILE N
ACC
LMEM
NIM
ISD HyperCube Network
CTR: ConTRoler
DMA: Direct Memory Access
NIM: Network Interface Module
(Makes network protocol translation)
NUMA
SHMEM
ACC: ACCelerator
LMEM: Local MEMory
SHMEM: SHared MEMory
NUMA: Non Uniform Memory Access
20 November 2009
WP4 Web Meeting
Slide 17 of 19
Fault Scenario Definition



Memory faults: a fault occurs randomly in shared data
memory (e.g. wrong value written). A read time, the
memory tells the reading tile that data contains errors. This
reading tile sends a message to the supervisor tile. The
supervisor takes actions to solve the problem.
Tile faults: a processing tile sends periodically a message
to the supervisor tile (watchdog). When it stops doing so,
the supervisor takes actions to solve the problem.
To solve a problem, the supervisor :




Stops the processing tiles
Find a new memory mapping and tile mapping.
Configure the network according to that mapping.
Restart the processing tiles
20 November 2009
WP4 Web Meeting
Slide 18 of 19
BACK
WP5 foreseen activities and deadlines

Supervisor : TILE 0
CTR
DMA
WP5: multicore chip FPGA implementation

M27: D5.2.2:

LMEM
VHDL IPs developed

NIM

Software developed


supervisor Tile, NIM, SHMEM controler, NoC
Tile bootloader, SHMEM test access
M36: D5.3.3




Several Tiles (12 foreseen)
Develop HAL
Reuse Operating Libraries from SystemC
Video detection application.