Transcript Slide 1

FinFET: a mature multigate MOS technology?
A wideband transistor simulation and
characterization approach
J.-P. Raskin1, T.M. Chung1, D. Lederer1, A. Dixit2, N. Collaert2,
T. Rudenko3, V. Kilchytska3, D. Flandre3
Université catholique de Louvain,
and 4Microelectronics Laboratories
Place du Levant, 3, B-1348 Louvain-la-Neuve, Belgium
[email protected]
1Microwave
2IMEC,
Kapeldreef, 75, B-3001 Leuven, Belgium
3ISP,
Kiev
Growing interest for MuG
• Strong limitations - Short Channel Effects - appearing
for Single Gate MOS below 50 nm
• Many technological difficulties to satisfy the ITRS
predictions, in terms of leakage current (IOFF), supply
voltage, Early voltage, DIBL, cutoff frequency, etc.
• Multiple-gate MOSFETs (MuG) are considered as
serious potential candidates
Planar MuG < > Non-planar MuG
Planar MuG
•
GAA: First planar DG MOS
– Isotropic wet etching of BOX
– good gate oxide-channel interfaces,
channel thickness controlled by highly
selective wet etching
– Need: variable W/L >< GAA (W/L=1)
•
Planar DG built by wafer bonding
starting with SG MOS
– Gate stacks are not built at the same
time (dissimetry)
– Misalignment of top and bottom gates
•
Planar DG built by transfer of a thin Si
film above a cavity
–
GAA
[Colinge, SOI Conf. 90]
SON-GAA, ST-M, IEDM’03
DG, CEA-LETI, SOI Conf. 04
Both gates are built simultaneously
– Misalignment of top and bottom gates
Self-aligned DG process, but no DG MOS yet
DG, UCL, SPIE 04
Non-planar MuG
FinFET, Triple gate
FinFET
IMEC, SSE’04
Omega gate, Pi-Gate
Taiwan Semicon., IEDM’02
RF analog factors of merit
• Several good published articles investigated the intrinsic behavior
of MuG experimentally and through simulations: ION/IOFF,
Subthreshold slope, Vth roll-off, DIBL.
• Analyses focused on RF analog performance – not limited to the
channel behavior (impact of parasitics related to the 3-D structure)
ITRS
Year
Lmin / node
(nm)
tox (nm)
gm/gds @ 5.Lmin
Parasitic cap.
(fF/µm)
fT (GHz)
2005
45 / 80
2.1
100
0.24
140
2006
37 / 70
1.9
100
0.24
170
2007
32 / 65
1.6
100
0.24
200
2009
25 / 50
1.4
100
0.24
280
2012
18 / 35
1.2
100
0.24
400
2015
12 / 25
1.0
100
0.24
700
Measured MuG
FinFET from IMEC
•
Gate lengths L from 10 µm down to 50 nm
•
Fin width Wfin from 10 µm down to 22 nm
•
Fin height Hfin from 60 to 95 nm
•
Fin spacing (Sfin) from 100 to 350 nm
•
Nitrided gate oxide of 2 nm EOT
•
NiSi salicide
Planar DG from UCL
•
SiO2 gate oxide of 30 or 6 nm
•
Si film of 87 nm
•
BOX = 400 nm
•
L from 20 down to 1 µm
Non-planar vs. planar MuG
3-D Atlas simulations of SOI MOSFETs Multiple-Gate Devices in
static and dynamic regimes
•
•
•
•
•
•
•
Single-, Double-, Triple-, and Pi-Gate MOS
L from 200 nm down to 25 nm
Hfin = 50 nm
Tsi = Wfin = 20 nm
Tox = 2 nm
Tbox = 150 nm
Channel doping = 1015 cm-3 (undoped)
Static simulation results
L
tSi
(nm) (nm)
200
20
100
20
75
20
50
20
25
20
Vth (V)
Vds
(V)
S (mV/dec)
DIBL (mV/V)
SG
DG
TG
PG
SG
DG
TG
PG
0.05
0.32
0.35
-
-
64.0
59.9
-
-
1.00
0.28
0.36
-
-
65.1
59.9
-
-
0.05
0.28
0.37
0.40
0.40
84.9
61.1
59.8
60.7
1.00
0.16
0.35
0.38
0.38
80.5
61.1
61.3
60.6
0.05
0.20
0.37
0.40
0.40
124.5
63.8
61.8
62.8
1.00
-0.095
0.34
0.38
0.38
110.1
64.4
62.7
63.1
0.05
0.045
0.35
0.39
0.40
198.5
77.3
75.3
74.2
1.00
-0.75
0.27
0.33
0.33
282.9
81.8
78.7
77.3
0.05
-
-
0.32
0.33
-
-
232.5
183.9
1.00
-
-
-0.35
-0.32
-
-
445.4
365.3
SG
DG
TG
PG
47
11
-
-
126
16
21
21
395
32
21
26
837
89
63
74
-
-
700
674
- Roll-off Vth , degradation of S and DIBL for SG for Lg < 100 nm
Solution: Reduce Si channel thickness (Vth control), but
technological problems in terms of uniformity and increase of Rs and Rd.
- Pi-gate present slightly better results, lower SCE
- At L = 25 nm, MuG with tSi = Wfin = 20 nm show degradation of their performance
Gm/Id: efficiency to convert DC to AC
Intrinsic voltage gain = Gm/Gd = Gm/Id x Id/Gd
= Gm/Id x VEA
Planar SOI SG and DG
FinFETs
Measurement results
1E+20
1200
-1
800
1E+16
600
1E+14
400
1E+12
Surface
Centre
200
1E+10
0
0.0
0.3
0.5
0.8
Vgs (V)
Undoped DG  and SG - - -
1000
100 nm DG MOSFET
• Clear interest for DG for channel length < 100 nm
• VI is not efficient at high Vgo
Simulation results
1.0
Mobility (cm V sec )
1E+18
2 -1
-3
Electron concentration (cm )
Volume inversion (VI)
Early Voltage vs Wfin and L
FinFETs
L = 10 µm
Measurement results
VEA for FinFET in VI regime is 10 x higher than for FD SOI
Intrinsic analog gain
Higher intrinsic gain for FinFET of around 20 dB compared to FD SOI MOS
Dynamic analysis of MuG
Simulation results
 At low Vgo, the gmMuG/gmSG and CgsMuG/CgsSG ratios are > 1
 At higher Vgo, no improvement on normalized gm for MuG over SG
 Volume inversion in MuG only efficient at lower Vgo
Miller capacitance Cgd
Measured Cgs/Cgd = 3
for 60 nm FinFET
 Cgs/Cgd: Ratio of Control capacitance of the channel to Parasitic
feedback Miller capacitance.
 MuG devices achieve a higher value of Cgs/Cgd as compared to SG
devices
3-D parasitic capacitances
Normalized Cgs
 Higher parasitic capacitances: TG > DG > SG due to more complex 3-D interconnection
 Main part of the parasitic capacitance is related to fringing field between
gate-to-source and gate-to-drain through BOX
Cutoff frequency
- For long L, fT of SG slightly higher
due to lower parasitic C compared to
MuG
- At small L, SG device, very high
SCE, leading to bad fT value
- Even MuG devices with L < 40 nm,
degradation appears
- To follow up the ITRS, we have to
reduce Wfin or tsi as well as EOT
(high-k)
Vgo = 500 mV and Vds = 1 V
Conclusions – Maturity of FinFETs?
FinFET: very promising technological solution at short term
Advantages:
Disadvantages:
- higher technological maturity than planar DG
- parasitic capacitances related to the 3-D FinFET structure
are only slightly higher than for SG
- reduced mobility for electrons (<110> cristalline orientation)
- control of Wfin by etching + gate interface quality
- higher source/drain resistances
Rs, Rd → reduced gm → lower fT and fmax
Rg → reduced fmax
Short term technological challenges: gate interface quality, silicidation S/D or
Low Schottky Barrier S/D contacts, integration density
Acknowledgements
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UCL clean rooms team
Mr. P. Simon for RF measurements
Dr. Jurczak Malgorzata’s group, IMEC
SINANO