Transcript LC VCO with One Octave Tuning Range

1
Design of an LC-VCO with
One Octave Tuning Range
Andreas Kämpe and Håkan Olsson
Radio Electronics-LECS/IMIT
Royal Institute of Technology (KTH)
SSoCC
April 12-13, 2003
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Introduction
VCO research has largely focused on reducing
phase noise, not tuning range.
Multi standard transceivers requires wideband VCOs
with low phase noise
Goal: Designing a VCO with one octave tuning
range while maintaining a low phase noise and
low power consumption.
SSoCC
April 12-13, 2003
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VCO topologies
LC tank
+ Low phase-noise.
+ Low power consumption
- Large chip area
- Tuning range (limited by CMAX/CMIN).
Delay element
Ring, transmission line, and
relaxation oscillators
+ Small chip area
- High phase noise and realativly
high power consumption.
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April 12-13, 2003
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VCO Architecture
Complementary structure (N & P) MOS =>
larger amplitude and symetric rise/fall time =>
Reduced power / phase noise
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April 12-13, 2003
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LC-tank and wide tuning range
One octave tuning range =>
Requires a Capacitance tuning
of 2 octaves.
- Tuning capacitor Cmax / Cmin > 4
(paracitcs: CP)
- Low voltage and large Cmax/Cmin =>
High varactor sensitivity (VCO gain) =>
sensitive to noise on the control line.
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f min 
2 L(Cmax  C p )
1
f max 
2 L(Cmin  C p )
Cmax  C p
f max
4
4
f min
Cmin  C p
April 12-13, 2003
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Discrete tuning
CMOS technology offers
excellent switches.
Bandswitching
The switched capacitors are used as band selectors (coarse tuning)
Channel selection is performed digitally.
+ Increased tuning range
+ Reduces the varactor gain => phase noise reduction.
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April 12-13, 2003
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Switch limitations (MOSFET)

Low capacitive load  Large tuning range
Minimum loss  Low power consumption
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April 12-13, 2003
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Trade-off
Loss or capacitive load.
Minimum loss = reduce Rds-on =
wide transistor with minimum gate length.
Minimum capacitive load = reduce Cgs /Cgd =
narrow transistor with minimum gate length.
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April 12-13, 2003
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Switch Optimisation
CTRL+
CTRL-
• NMOS transistors (higher transconductance).
• Drain / source are AC coupled (band sw cap)
and biased via resistors => maximizes (Vgs-Vt)
=> Reduced Rds-on
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Switch On
1.
+
8
V
-
0V
1.8 V
Switch on: Vgs = 1.8 V => Minimum RDS
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April 12-13, 2003
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Switch Off
1.
-
8
V
+
1.8 V
0V
Switch off: Vgs = -1.8 V => 20%
reduction in capacitance compared to
having Drain and Source biased at 0 V.
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April 12-13, 2003
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Capacitor array
C
C
W
4R
4R
B0
2C
2C
2W
2R
2R
B1
4C
4C
4W
R
R
B2
3bits binary weighted Capacitor array.
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April 12-13, 2003
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Varactor
Cntrl+
Cntrl-
• Accumulation-mode mos varactors =>
Less steep voltage to capacitance transfer.
• 4 varactors are conected anti parallell =>
Differential operation and control =>
Common mode rejection
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April 12-13, 2003
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Inductor
+ Differential inductor
(increased coupling).
+ 3 metal layers (M6, M5, M4)
are stacked on top of each other
=> reduces the series resistance.
=> increased Q
- Increased capacitive load
(Lower metal layers are closer to
the substrate).
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April 12-13, 2003
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Inductor simulations
15
3.80E-9
14
Q
3.75E-9
12
3.70E-9
11
3.65E-9
Inductance
inductance (H)
Q
13
10
9
3.60E-9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
Frequency (GHz)
Optimized and designed with ASITIC and ADS.
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April 12-13, 2003
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Inductor model
MUTIND
• Lumped model of a transmission line.
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April 12-13, 2003
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Inductor-model simulations
(%)
Real(S)
s11error s12error s22error s21error
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
1.2
1.4
1.6
2.0
1.8
Frequency (GHz)
2.2
2.4
2.6
Lumped model error ”Real(S)”.
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April 12-13, 2003
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Inductor-model simulations
(%)
Imag(S)
s11error s12error s22error s21error
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
1.2
1.4
1.6
1.8
2.0
Frequency (GHz)
2.2
2.4
2.6
Lumped model error ”Imag(S)”.
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April 12-13, 2003
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Amplitude Variations
The oscillation amplitude varies considerably across the wide tuning range
Vo 
4

T hus:
 I tail  RT and RT  Rs  QT2 ,
Vo 
4

 I tail
whereQT 

o  L 2

  2 !!
Rs
o
o  L
Rs
.

 In practice Vo  o
Requires an adjustable negative resistance =>
Achieved by controlling the biasing current.
gm 
1
2COX
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W
ID
L
April 12-13, 2003
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VCO
VDD
Varactor
The band selection also
controlles the biasing
current. => Constant
oscillation amplitude over
the entire tuning range.
I0
SSoCC
I1
I2
April 12-13, 2003
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Tuning range
(GHz)
000
001
010
011
100
101
110
111
2.7
2.6
2.5
Frequency
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
-2.0
-1.0
0.0
1.0
2.0
Differential control voltage (V)
Large tunability 1.2 GHz – 2.6 GHz.
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April 12-13, 2003
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VCO’s
2
 f 
FOM  S SSB    PVCO / m W
 f0 
Tech
[um]
Tuning
range
[%]
FOM
[dBc/Hz]
“A 5.9 GHz Voltage-Controlled Ring Oscillator in 0.18 μm CMOS”, IEEE J.
Solid-State Circuits 39, pp. 230- 233, Jan 2004.
0.25
18
-183
“A 1.8 GHz higly-tunable low phase-noise CMOS VCO”. Custom Integrated
Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000, pp. 585588. 21-24 May 2000.
0.25
28
-183
”New wideband/dualband CMOS LC voltage-controlled oscillator”. Circuits,
Devices and Systems, VOl 150. Proceedings of the IEEE 2003, pp. 453459 6 Oct 2003.
0.25
98
-158.3*
“A 15-mW Fully Integrated I/Q Synthesizer for Bluetooth in 0.18 μm
CMOS”, IEEE J. Solid-State Circuits 38, pp. 1155 - 1162, July 2003.
0.18
16
-174.5*
“Design of Wide-Band CMOS VCO for Multiband Wireless LAN
Applications”, IEEE J. Solid-State Circuits 38, pp. 1333 - 1342, August
2003.
0.13
SOI
58.7
-186.6
0.18
74
-190
VCO
This
SSoCC
* Quadrature VCO
April 12-13, 2003
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Conclusions
• It is possible for a VCO to have a large tuning range
combined with a low phase noise and low power
consumption. This design has a very good performance
expressed in FOM (-190 dBc/Hz/mW) and superior if the
wide tuning range is taken in account.
• Large chip Area, due to many capacitors and a large
inductor. If the oscillator was designed to be operated at a
higer frequency, the Chip area could be decreced (smaller
LC tank) The down side is an increaced loss in the
switches (capacitor array).
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April 12-13, 2003
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Complementary or NMOS-only 1
ID(n + p) = ID(n-only)
Equal gm: gm(n + p) = gm(n-only)
gm 
1
2COX
SSoCC
 pW p  nWn  nWnonly
W
ID
L
April 12-13, 2003
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Complementary or NMOS-only 2
Symetric rise/fall time:
CLOAD ( n  p )
n
WP 
 Wn  3Wn
p
3
W p  Wn  only
4
1
Wn  Wnonly
4
3
1
 K  (Wp  Wn )  K  ( Wn  only  Wn  only )  K  Wn  only
4
4
CLOAD ( nonly)  K Wnonly
SSoCC
April 12-13, 2003