Transcript Definition of Reactive Systems using the Waveform

Racal Research
Definition of Reactive Systems using
the Waveform Description Language
E.D.Willink, Racal Research Limited,
[email protected],
http://www.rrl.co.uk/projects/wdl/wdl.html
FM3TR Radio Forum,
24th October 2000,
UK Programmable Digital Radio (PDR) Phase 1,
Waveform Description Language (WDL) programme
(DERA contract CU009-0000002745)
Raytheon, Communication Systems Division, Fort Wayne, Indiana,
Racal, Racal Research Limited, England
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Introduction
WDL and Specifications
Examples (from FM3TR)
Architectural Mapping (JTRS)
Summary
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WDL Antecedents
Object
Oriented
Languages
Functional
Languages
expressions
types
Block
Diagram
Languages
State
Machine
Languages
classes
data flow
Waveform
Description
Language
events
states
semantics
Reactive
Languages
constraints
Specification
Languages
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Specification or Implementation
Implementation
How it can be done
Specification
What needs to be done
Waveform Description Language (WDL)
Implementation practices re-applied in the
specification domain
One specification
Many alternate implementations
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WDL Products
WDL
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Simulation
Environments
Execution
Environments
HLA,
Ptolemy,
...
Application,
Process,
CORBA Component,
FPGA,
Analogue hardware,
...
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Specification of Systems and Subsystems
subsystems exist at many scales
telecomms - international / national / regional / local / internal
equipment - cabinet / rack / module / board / component
CORBA components support two scales
inside
outside
WDL
fully encapsulated
same approach at all scales
WDL specifies without implementing
WDL may be refined from a specification to an implementation
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Specification of Communication
High level systems
sporadic control events
Low level systems
intensive calculation
‘continuous’ communication
WDL
sporadic and continuous flows are supported
continuous and discrete time are interchangeable
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Complete specification (Low Level)
Amplifier - relatively easy
vout = 10 * vin
In practice need constraints
frequency < 1 GHz
load impedance 50 Ω ± 10%
third harmonic ...
WDL
mathematical definition of the ideal behaviour
constraints to bound permitted behaviour
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Complete specification (High Level)
System specifications - very challenging
large, unreadable
Informal specification
terse - omissions lead to ambiguities
verbose - duplications lead to contradictions
Formal specification
good in principle
impractical for real applications
unapproachable for most practitioners
WDL
pragmatic compromise
formalisable, modular, familiar, practical, acceptable
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Specification in WDL
Progressive decomposition
systems - subsystems - components - building blocks
Single hierarchical perspective
clear readable specification
removes ambiguities, avoids contradictions
Implementation in WDL
Progressive refinement of specification
further decomposition
practical constraints
recomposition
Minimal refinement
executable reference model
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WDL Transformations
Decomposition
Text
Editors
Refinement
WDL Specification
Refiner
Schematic
Editors
WDL Program
Checker
WDL
Compilers
WDL Products, Waveform Bundle
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Implementer
Sponsor
WDL
Refinement
Abstract Specification
layers
coders
modulators
Actual Specification
algorithms
parameters
bit-truth
Reference Model
precisions
acquisition algorithms
System Design
filter characteristics
acquisition algorithms
minimum precisions
System Configuration
filter characteristics
decimation ratios
Hardware Mapping
partitioning
library matching
WDL Specification
Component Configuration
parameterisation
actual precisions
bit-truth
WDL Program
Reference Model
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Refinement
Abstract WDL specification (unimplementable)
Waveform sponsor refines to support
a reference model
System designers refine to support
hardware partitioning
analogue/digital partitioning
concrete filter designs
specific acquisition strategies
apportion implementation loss budgets
Implementers refine to
exploit pre-existing object libraries
compensate for compiler limitations
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Hierarchical decomposition
Entity
module of specified behaviour
not necessarily an implementation object
Message
user defined data types (and array shapes)
four scheduling flow types
Hierarchical Diagrams
message flow diagrams
statecharts
Leaf specification
mathematical definition
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(UML) Statechart
StateChartEntity
event
guard
out
State1
event[guard]
/out(...)
WDL extension to UML:
state behaviour may be a
message flow
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State2
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MessageFlowEntity
Message
Flow Diagram
in1
in2
out
Entity2
in1
in
out
in2
Entity1
in1
in2
out
out
WDL Message Flow Diagram
each arc has defined data and flow type, connecting at ports
each entity is self-scheduling - rendezvous of relevant ports
external ports to define hierarchy
cf. UML Collaboration diagram
external scheduling, connection points have no semantics
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data_in
FM3TR
Protocol
Layers
Fm3tr
data_in
data_out
voice_in voice_out
antenna
Nwk
Hci
nwk
data_out
data_out
out_to_dlc
Dlc
dlc
in_from_nwk
hci
rx_from_mac
out_to_nwk
tx_to_mac
Mac
Application
Presentation
data_in
hci
in_from_dlc
mac
Session
tx_from_dlc
rx_to_dlc
hci
rx_from_phl
carrier_detect tx_to_phl
Transport
Network
Phl
Data Link
Physical
phl
voice_in
tx
hci
voice_in
rx
carrier_detect
antenna
voice_out
antenna
voice_out
OSI layers
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Phl
FM3TR Physical
Layer
tx
hci
voice_in
Cd
Hci
t_cd_on
t_cd_off
carrier
t_cd_on
hci
tx_inc t_cd_off
config
rx_inc
crc_inc
hci
detect
carrier_detect
Rx
Tx
tx
rx
carrier_detect
voice_out
antenna
tx_inc
out
in
in
rx_inc
crc_inc
out
rx
Fsm
config
tx
trans_sec
TransSec
trans_sec
carrier
rx
voice_out
voice_out
Radio
Ptt
voice_in
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voice_in voice_out
reset
voice_in
rf_in
rf_freq
rf_out
reset
rf_freq
rf_out
antenna
rf_in
antenna
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FM3TR
Physical
Layer
State
Machine
VOICE_TX
config
voice_in
tran_sec
VoiceTxFsm
TxModulator
config
amplitude
voice
phase_change
tran_sec
rf_freq
amplitude
rf_out
phase_change rf_freq_out
rf_freq_in
carrier
exit
rf_out
rf_freq
carrier_detect
voice_in[ptt]
RX
entry / reset()
RxFsm
config
rf_in
config
rx
rf_in
voice
rf_freq carrier
rx
voice_out
carrier_detect
RxModulator
tran_sec
tran_sec
rf_out
rf_freq
rf_out
rf_freq
Sink
Fsm
tx
voice_in
rf_in
config
tran_sec
rx
carrier
rf_out
rf_freq
voice_out
reset
voice_in
in
tx
exit
DATA_TX
config
packet
tran_sec
DataTxFsm
TxModulator
config
amplitude
data
phase_change
tran_sec
rf_freq
amplitude
rf_out
phase_change rf_freq_out
rf_freq_in
carrier
rf_out
rf_freq
carrier_detect
Sink
voice_in
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TUNING_TIME
Hop Modulator
GuardModulator
config
hop
modulation
modulation
after(config.tuning_time)
HopModulator
hop
config
config
hop
RISE_TIME
modulation
RiseModulator
config
hop
config
hop
modulation
modulation
after(config.rise_time)
INFORMATION
InfoModulator
config
hop
config
hop
modulation
modulation
exit
FALL_TIME
FallModulator
tuning
time
rise
time
information
time
fall
time
config
hop
config
hop
modulation
modulation
after(config.fall_time)
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Hop
Rise
Time
RiseModulator
config
hop
modulation
F(t)
out
amp
Constructor
Constant
out
shift
amplitude
frequency_shift
frequency
modulation
modulation
Constant
out
freq
constraint: shift.out = 0;
constraint: freq.out = hop.frequency;
constraint: amp.out = range
{
minimum 0;
value 0.5 * (1 - cos(2*pi*t/config.rise_time));
maximum 1;
};
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Language for specification
need expressions for
configuration constraints, state machine guards
need statements for
state machine actions
need types for
messages
need a language
implementation languages do not specify
specification languages are unapproachable
specification languages have unhelpful focus
new language is new
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Specification
Subtractor
minuend
subtrahend
entity Subtractor
{
in minuend;
in subtrahend;
out difference;
response minuend subtrahend
{
specification
{
difference(minuend - subtrahend);
};
};
};
difference
// Whenever a rendezvous of
// minuend and subtrahend exists
// receive minuend and subtrahend
// subtract values
// send to difference
Polymorphic
type, shape, flow, language
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Hardware Mapping
Dedicated hardware
direct compilation
one ‘executable’ per ‘execution unit’
General Purpose ‘Virtual’ hardware - software radio
CORBA components
software processes
HLA entities
identify components and messages
indirect compilation
one executable per component per platform
one interface declaration per message
configuration profiles per application
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Din
data_in
Dout
data_out
HtoN
Nwk
Hci
data_in
hci
in_from_dlc
nwk
FM3TR
Layers
as
JTRS
Components
and
Messages
Fm3trNetwork
out_to_dlc
NtoD
DtoN
HtoD
Dlc
in_from_nwk
hci
rx_from_mac
dlc
out_to_nwk
Fm3trLink
tx_to_mac
DtoM
MtoD
HtoM
Mac
tx_from_dlc
rx_to_dlc
hci
rx_from_phl
carrier_detect tx_to_phl
mac
Fm3trModem
HtoP
Phl
phl
Fm3trHci
voice_in
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data_out
tx
hci
voice_in
Vin
rx
carrier_detect
antenna
voice_out
Vout
antenna
voice_out
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JTRS Mapping
Fm3trHci
Fm3trModem
Fm3trModem.Phl.nonTranSec
Fm3trModem.Mac
DSP Executive
Board Support Package
CF Core
DomainManager
C++ CORBA DeviceManager
ORB and
File Services
Services
Logger
Timer
Device
Posix RTOS
Network Protocol Stacks
Board Support Package
Fm3trNetwork
Fm3trModem.Phl.TranSec
Fm3trLink
INFOSEC Algorithm
Black
Red
INFOSEC
INFOSEC
Adapter
Adapter
Posix RTOS
DSP Executive
Network Protocol Stacks
Board Support Package
CF Core
DomainManager
C++ CORBA DeviceManager
ORB and
File Services
Services
Logger
Timer
Device
Posix RTOS
Network Protocol Stacks
Board Support Package
Black cPCI
Modem
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Red cPCI
Black Control Processor
INFOSEC
Red Control Processor
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WDL & JTRS Summary
JTRS
a common radio architecture for waveform development
modelled after very successful PC paradigm
allows third party development of low cost applications
WDL
efficient methodology for developing many waveforms
provides unambiguous specification
provides portable implementation
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Summary
WDL specifies a determinate behaviour
Decomposition to manageable sub-specifications
Refinement to support a reference model
Refinement to support product implementations
Polymorphism to exploit generic libraries
Realistic scheduling models
Type-oriented code generation for flexibility
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Status
Phase 1
Initial consideration of language concepts
Example decomposition of FM3TR (1 month)
clearer
many anomalies reported back
Future
Better quality specifications
sponsor provides reference model
Semi-automated code generation
months rather than years
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