Transcript Development of Low-mass, Radiation

Development of Low-mass, Radiation-hard, Fast Silicon Pixel Detectors
based on Monolithic CMOS Technology
HI-MAPS
Joint Research Project for the EU
FP 6/I3 HP
Budget, first draft of application
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What we apply for!
Item
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What we can provide!
Institute
Scientists
FTE
Salary
IReS
senior scientist
0,75
300 k€
Univ.
Frankfurt
postdoc
1
200 k€
“
senior scientist
0.25
100 k€
Univ. Krakow
senior scientist
0.5
200 k€
GSI
postdoc
0.5
100 k€
senior scientist
0.5
200 k€
3.5
1100 k€
sum
Cost
Manpower (2 Postdocs, 5PhD
Students)
940 k€
Design
(Engineering runs, microcircuit testing device, readout boards):
300 k€
Dedicated equipment
(probe stations, test
setups; tools, sundries):
200 k€
Travel
100 k€
sum
1540 k€
Proposal of JRP on Solid State Detectors
Silicon detectors (G. Stefanini/CERN)
now including amorphous hydrogenated silicon (a-Si:H)
(P. Jarron/CERN)
Monolithic Si pixel detector (J. Stroth/GSI)
Diamond detectors (E. Berdermann/GSI)
Joint Research Project for the EU
FP 6/I3 HP
Rationale of the Merging
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Common objectives in the development of detectors and associated electronics
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Common challenging problems
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Low material budget, low power, high integration, high speed, radiation hardness
Low mass mechanical supports and cooling system, interconnects (E/O), reliability
Detector technologies with different levels of maturity
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Hybrid Si pixels
state of the art
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Amorphous Si detectors
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Monolithic Si pixels
early prototyping
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Diamond
new: single crystals (high CCE), potential for very
high speed and radiation hardness
novel, proof of principle (a-Si:H layer on ASIC)
Joint effort to acquire and share new knowledge, methods, access to facilities,
expertise
Compare test results and performance with established bench marks
Contribute to innovation in specific technologies, improve the definition of requirements
and performance assessment, facilitate the decision process
Hybrid vs. Monolithic
Sandwich of a sensor substrate bump
bonded to the readout chip
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High Resolution
High rate
Radiation hard
Sparse data scan
but
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Based on CMOS light sensors. With integrated
signal processing on the same substrate.
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Material budget (x/X0  1 %)
Complex fabrication
but
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Highest Resolution
Minimal pixel size
Cheap
Low mass
Moderately radiation tolerant
Slow
Maybe a-SI:H !!!
amorphous-Si:H Detectors
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Experimental high rate
Reactor at IMT Neuchatel
T deposition in plasma 220 C
4 x 4 mm
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ITO
2 x 2 mm
a-Si:H
Cr
1.5 x 1.5 mm
Glass
1 x 1 mm
0.5 x 0.5 mm
0.2 x 0.2 mm
slide by courtesy of G. Stefanini, CERN
First experimental pixel a-Si:H
deposited on a fast readout ASIC
a P.I.N is formed: P and N ultra thin
Collection in the thick I layer
First results with a-Si:H detector demonstrator
(P. Jarron - unpublished)
Excitation pulse 2ns width from laser l = 660nm
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Input charge ≈ 2 fC ≈ 12,000 electrons
a-Si:H layer thickness 13mm, bias voltage 70V (depletion)
Single shot 1fC signal
Rise time 6ns
FWHM: 25ns
ENC 250 rms electron
slide by courtesy of G. Stefanini, CERN
Signals measured
on 13 pixel
100mm x 100mm
Charge collection
70% in 40 ns
First results with a-Si:H detector
demonstrator (II)
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Proof of principle established
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detector with a-Si:H layer on top of IC
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in
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rise time 6 ns, signal width 25ns
slow signal tail limited to 200ns (transport of holes and electrons
deep states)
First lab performance test
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very low bulk leakage current <1nA/cm2
edge leakage current 500nA caused by imperfect lift off
stability: tested over several days operation with bias on
good uniformity pixel to pixel
Objectives for a-Si:H Detector Development
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Optimize a-Si:H material quality for hadron detector
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Optimize high deposition PECVD rate reactor
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Minimize unpassivated defects, minimize internal mechanical stress for large area detector
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Optimize process for very high field
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Characterise charge transport
Radiation hardness: expected to exceed 1015 p/cm2 thanks to spontaneous annealing of defects
with
hydrogen (≈ 15% of mass in a-Si:H) - to be tested
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Develop lithography technology for ‘above IC’’
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Adapt patterning and masking technique, develop metallurgy of contact
Develop readout ASIC to detect charge packets of 100 to 1000 e
Optimized layout technique for ‘above IC’ technology
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Ultra low power CMOS circuit, readout architecture adapted to high density pixel
Manufacture demonstrators and prototypes
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Large area samples of a-Si:H layer on ultra thin substrate
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Linear array of a-Si:H pixel detector 25 micron pitch
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2D a-Si:H pixel detector 25 micron pitch
Objective
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Verify the applicability of MAPS for high rate,
high-multiplicity nuclear experiments
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Increase readout speed
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Improve radiation tolerance
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Data driven, 107 interactions/s
on-chip sparsification/buffering
Fluence up to 1016 n/cm2
Reduce material budget
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Detector, support, cooling (low power designs), data transport
Network Partners
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Heavy Ion & Hadron
Physics
L.N.S.
Monolithic Active Pixels
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Industrial
companies
Centers of
Excellence
M. Winter et al., IReS
MIMOSA
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Prototype chips developed at IReS in
collaboration with LEPSI
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no performance degrading up to 1012 n/cm2
MIMOSA 6 first chip with sparsification on the
chip available end of 2002 (now)
M. Winter et al., IReS
Facts after 1st round of simulations
Beam pipe of 1 cm Ø
Fluence above 1016
Pixel
Strip
CBM Silicon Working Group
Institute
Members
Expertise
MSU/SINP,CBKM
Moscow
3
Silicon Strip detectors (design, assembly)
Univ.
Krakow
2
Silicon for medium energy experiments
IRES
Strasbourg
3
MAPS
Klopin
St. Petersburg
1
Space frames, cooling
LBL
Berkeley
2
CMOS thinning
GSI
Darmstadt
4
CMOS design, DAQ
IKF
Frankfurt
2
Plans to set up " silicon work shop"
Next steps to take
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2nd generation of simulations
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refine geometry
define acceptable thickness
Define working packages
Prepare 1st CBM-Silicon working group meeting