Transcript Document

Layout Considerations of Non-Isolated
Switching Mode Power Supply
Presented by
Henry Zhang
Power Business Unit
Linear Technology Corp.
Oct. 2003
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
1. General Discussion
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
Plan of the Power Supply Layout
• In the system, power supply should be close to
its load devices.
• Cooling fan should be close to the supply to limit
its component thermal stress.
• Select the right number of layers and copper thickness
• The large size passive components (inductors, bulk
capacitors) should not block air flow to power MOSFETs
• Power supply designer should always works closely with
PCB designer on the critical layout design
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
4-Layer PCB – Layer Placement
Desired
Undesired
Layer #1 – Power Component
Layer #1 – Power Component
Layer #2 – Small Signal
Layer #2 – GND
Layer #3 – GND
Layer #3 – Small Signal
Layer #4 – Small signal / controller
Layer #4 – Small signal / controller
High current loop
Pulsating current loop
PCB capacitance
• Place ground or DC voltage layer between power layer and
small signal layer
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
6-Layer PCB - Layer Placement
Undesired
Desired
Layer #1 – Power Component
Layer #1 – Power Component
Layer #2 – Small signal
Layer #2 – GND plane
Layer #3 – GND plane
Layer #4 – DC Voltage or GND plane
Layer #5 – Small signal
Layer #3 – Small Signal
Layer #4 – Small Signal
Layer #5 – DC Voltage or GND plane
Layer #6 – Power Component / Controller
Layer #6 – Power Component / Controller
• DC power and ground planes function as AC reference
planes.
• As a general rule, the reference planes of a multi-layer PCB
design should not be segmented.
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
Small Signal Traces on Reference Layer
• If the small signal traces have to be routed on the reference
layer, use short traces with proper direction:
Desired
Reference Layer
Undesired
Reference Layer
current
current
Coupled AC
current return path
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
Copper Thickness and PCB Resistance
Copper resistivity (/cm): S ( T )  1 . 724  10
6
 [1  0 . 0039  ( T  20 )]
T – Copper temperature in oC
Resistance of copper:
R (T ) 
S ( T )[  / cm ]  Length [ cm ]
Width [ cm ]  Thickness [ cm ]
S ( T )[  / cm ] 

1000 mils
 Length [ mils ]
2 . 54 cm
Width [ mils ]  Thickness [ mils ]
Example: 1 Oz copper (1.4 mil thick), 0.5 inch wide (500mils), 2 inches long
(2000mils), at 70 oC with 20A current:
Rcopper = 2.3 m, Vcopper=46mV, Ploss=0.92W
High current application - Recommend 2 oz or higher for external power layers
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
2. DC/DC Converter Power Stage Layout
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LTC Company Confidential
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Buck Converter Current Paths
Continuous Current
VIN+
Pulsating Current
ST
High dv/dt node
ESRin
Vin
Cin
LF
SW
CHF
ESRo
SB
D
Co
R
Vo
PGND
• Identify the continuous and pulsating current paths
• Pay special attention to pulsating current paths and high
dv/dt switching node
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
Parasitic Inductance in the Current Paths
and Example Layout (Buck)
Trace Inductance
VIN+
LF
ST
ST
SB
SW
VIN+
SW
D
CHF
CHF
SB
PGND
D
0.1uF – 10uF
Ceramic Capacitor
Minimize this
loop area
PGND
• Minimize loop between HF capacitor and MOSFETs
• It is desirable to keep CHF, top FET and bottom FET on the same layer
• Use multiple vias for power connection
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
Boost Converter Current Paths
Continue Current
High dv/dt node
LF
VIN
CIN
SW
Pulsating Current
D
SB
Vo+
Vo
CHF C
o
Load
PGND
• Minimize the critical pulsating current loop on the output side
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
Output Noise Decoupling Capacitor (Boost)
LF
D
SW
SB
LF
SW
D
SB
CHF
Vo+
CHF
PGND
0.1uF – 10uF
Minimize this Ceramic Capacitor
loop area
PGND
(b)
(a)
• Minimize the critical pulsating current loop on the output side
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LTC Company Confidential
[email protected], 3863
12V-to-2.5V/30A LTC3729 Supply Layout Example
VIN+ (12V)
VO+ (2.5V)
LF1
QT
CIN
SW1
LTC3729
Co
QB
GND
GND
Co
SW2
VIN+
VO+ (2.5V)
(a)
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Noise Problem @ Heavy Load
Io = 0A
Io >= 13.3 A
vSW1
iLF1
vSW2
(c)
(b)
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LTC Company Confidential
[email protected], 3863
Input Ceramic Capacitors Make a Difference
V IN + (1 2 V )
Add
1uF/16V/X7R
V O + (2 .5 V )
L F1
QT
C IN
SW 1
LTC3729
Co
QB
GND
GND
Co
SW 2
V IN +
V O + (2 .5 V )
Io = 0A
(a)
Io = 30 A
vSW1
iLF1
vSW2
(b)
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(c)
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Land Patterns of Power Components
Desired
Undesired
-
+
R/C/D/L
C
-
+
C
R/C/D/L
FET
Connected Via
Connected Via
• Use wide / short copper trace for power components
• Use multiple vias for inter-layer connections
• Avoid improper use of “thermal relief”
• Minimize resistance and inductance
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LTC Company Confidential
[email protected], 3863
3.3V/40A LTC3729 Layout Design Example
R1 2
High Current Trace
Cse n 1
1 0 00 p F
100
R1 3
VIN
C1 4
0 .1 u F
10
12V
100
J1
5 6 7 8
R3
QT 1
S i7 8 60 D P
CH F1
1uF
+
CI N
100UF/16V
4
IN TV CC
24
P GOO D
RU N/S S
C7
0 .1 u F
5
6
7
8
R2
IN TV CC
IT H
B OOS T2
T G2
V DIF FO UT
C2
E AI N
2 2 0p F
Ct h p
1 2 0p F
C1
1 8 0p F
R1
8 .0 6 K
S GND
B G2
SW2
S EN SE 2+
S EN SE 2V OS +
V OS -
D2
21
3
4
C6
0 .0 0 2 OH M
0 .4 7 uF
1 2 3
B AT 54 A
2
QT 2
C9
1
18
16
D1
MB RS 34 0
5 6 7 8
0 .4 7 uF
S OT -23
V O UT
3 . 3V @ 4 0A
CH F2
1uF
S i7 8 60 D P
J2
4
19
17
14
13
12
11
L2
0 .5 6 uH
Rse n 2
1 2 3
CO UT 1
+
5 6 7 8
QB 2
2 xSi7 85 6 DP
0 .0 0 2 OH M
4 x 330uF/4V
Sanyo POSCAP
D3
MB RS 34 0
4
GND
J3
3
2
Ct h
5 6 0p F
9
P GND
4
20
2 5 .5 K
N/ C
22
3
2
28
25
26
27
23
Rse n 1
5 6 7 8
QB 1
2 xSi7 85 6 DP
E XT VC C
S EN SE 1S EN SE 1+
NC
B OOS T1
SW1
T G1
B G1
0 .5 6 uH
1
Rt h
14K
10
P LL I FL TR
P LL I N
L1
1 2 3
3
2
1
V IN
15
C5
1uF
10V
1
U1
C4
+ 4 .7 u F
16V
1 2 3
L TC 39 2 9 EG
R8
Cse n 2
1 0 00 p F
100
R1 1
Sign al G roun d
100
Pow e r G roun d
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LTC Company Confidential
R9
10
R1 0
10
V S EN +
J4
V S EN -
J5
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Examples of a 2-Phase DC/DC Power Stage
Air Flow
D
GND
QB1
CHF1
QT1
Vo
QB1
SW1
Cout
Cout
CIN
Cout
GND GND
L2
QT2
CHF2
GND
Rsen2
SW2
QB2
QB2
Rsen2
Rsen1
L1
VIN
Cout
CIN
Henry J. Zhang, Oct. 2003 FAE Meeting
D
GND
QB1
CHF1
QT1
QB1
Cout
SW1
Rsen1
L1
D
Internal
GND Layer
Vo
L2
Vin
Internal
GND Layer
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Separation of Input Paths Among Supplies
Desired
Undesired
RPCB1
RPCB
DC/DC
#1
Cin
DC/DC
#1
PGND
DC/DC
#2
Cin
RPCB2
PGND
PGND
DC/DC
#2
PGND
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
3. Layout of the Controller and MOSFET
Drivers
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
Decoupling Capacitor and Separated Grounds
LTC3729
RUN/SS
R
RSENSE
C
R
C
SEN1+
TG1
SEN1-
SW1
EAIN
SGND Island
C
BG1
ITH
INTVCC
VDIFF
BG2
SW2
RSENSE
R
R
SEN2C
C
SGND PGND
PGND
Plane
TG2
SEN2+
Shortest Distance
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
Signal Ground and Power Ground
• Components connected to following pins use SGND:
- EAIN, RUN/SS, ITH, UVADJ, PHAMD, PLLIN, PLLFTR, FCB, CLKOUT
•Components connected to following pins use PGND:
- BOOST, +5V, PGND
•The SGND and PGND can be tied together underneath the IC.
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
QFN Package Controller Layout
Example
LTC3731
PGND
SGND
SGND
INTVCC
C
PGND
PGND
Vias
Vias
• Exposed SGND pad must be soldered to PCB
• Use multiple vias to connect SGND pad to both SGND
and PGND layers
• PGND pin also connects to SGND pad underneath the IC
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
Gate Driver Traces
LTC3729
Route together
QT
BOOST1
TG1
SW1
INTVCC
BG1
QB
C
PGND
Automatically coupled AC
ground return current
PGND
Plane
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
IC Signal Trace Width
Following are the trace width values we use in
Polyphase demo board:
20 mils – TG, BG, SW
25 mils - +5V, Vcc, PGND
15 mils – Current sensing, feedback, ITH, etc.
10 mils – Short traces that directly connected to IC pads
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
Current Sensing Traces
RSENSE
LF
Vo+
Direct trace connection.
Do NOT use via.
LTC3729
R
SENSEC
R
This via should NOT
touch any other internal Vo+
copper plane.
SENSE+
• Kevin sensing of the current signal
• Keep current sensing traces away from noisy traces / copper
area or use ground layer for shielding.
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
Sensitive Traces and Noisy Traces
• Most sensitive traces:
Current sensing (SENSE+/-), EAIN, ITH, SGND
-Sense+ / - traces for each channel should be routed together
With minimum trace spacing. The filter capacitor should be as close to
IC pins as possible. The filter resistor should be close to filter capacitor.
- Keep sensitive traces away from noisy traces.
• Sensitive traces:
Vos+/-, DIFFOUT, PLLFTR, CLKOUT
-CLKOUT is a sensitive trace but it is also a noisy trace. So keep it away from
other small signal sensitive traces.
• Most noisy traces:
SW, TG, BOOST, BG
-Keep them away from sensitive traces.
-Avoid overlapping between large SW copper area and sensitive traces in two
neighborhood layers.
- For each channel, route the SW and TG trace together with minimum space.
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863
Summary - Layout Checklist
• Plan of the layout:
– Location of the supply / load / bulk capacitors
– # of layers / layer placement / copper thickness
• Power stage layout:
– Power component placement
– Power component land patterns
– Identify pulsating current paths
– Decouple capacitor close to MOSFET
– Short / wide copper trace and multiple vias for high current
• Controller circuit layout:
– Decoupling capacitors close to pins
– Separate signal / power grounds
– Current sensing
– De-couple sensitive and noisy traces
– Gate driver traces
– Select proper trace width
Henry J. Zhang, Oct. 2003 FAE Meeting
LTC Company Confidential
[email protected], 3863