Transcript Hardware Overview and Initialization

Hardware Overview
Net+ARM – Well Suited for Embedded Ethernet
Single and Multiple Processor Environments
Understand the System on a Chip
Net+ARM Performance
Why the NET+ARM is Well Suited
for Embedded Ethernet Projects …
ARM7 CPU
Cache
RAM
Cache
Utilization
Cache Control
Ethernet
Serial
ENI
1284
GPIO
Network
DMA
MEM &
BUS
External RAM
NET+ARM™ System Overview
Single Processor Environment
Reset
Power
FLASH
Clock
RAM
Shared RAM
FIFO
Additional I/O
Optional
Co-Processor
Interface
•SDRAM
•EDO DRAM
•FP DRAM
•SRAM
JTAG
ENI Interface
Three Additional Chip Selects
Available for External Hardware
UART, HDLC, SPI
Supported…
Serial Port
Line Driver
8, 16, or 32 Bit Peripherals
Independently Configured
External Bus Master Capable
RS232, 422, 485
DMA Support
Serial Port
Line Driver
Serial Interface
JTAG
Physical
Layer
Transformer
DMA Support
DMA CAPABLE
RJ45
Network
NET+ARM™ System Overview
Multiple Processor Environment
Data movement to / from external processor
Power
Reset
FLASH
RAM
ENI
External
Processor
JTAG
•SDRAM
•EDO DRAM
•FP DRAM
•SRAM
FLASH
Three Additional Chip Selects
Available for External Hardware
RAM
8, 16, or 32 Bit Peripherals
Independently Configured
External Bus Master Capable
JTAG
•Shared RAM
•Up to 64K of NET+ARM
RAM designated
•FIFO
•Two 32 Byte FIFOs
supported by DMA
•NET+ARM ENI
INTERFACE is a SLAVE
DMA CAPABLE
Serial Interface
Physical
Layer
Transformer
DMA Support
RJ45
Network
Understanding the SoC
Peripherals
GEN Module
Interrupt
DMA
ENI
Ethernet
Controller
ARM7
Core
Timer
GPIO
Cache
Clock
Serial
Controller
Memory
Controller
Peripherals
Bus
Controller
Bus
Arbiter
NET+ARM™ Performance
(X32 SDRAM with Multiple DMA Channels)
TYPICAL DESIGN
BUS MASTERING
11
POTENTIAL BUS MASTERS 
11
11
ARM7
DMA
4-1-1-1
4-1-1-1
ENI
External
EACH BUS MASTER IN THE
CURRENT CYCLE CAN MOVE
4 LONG WORDS… MUST THEN
GIVE UP THE BUS IF ANOTHER BUS
MASTER IS WAITING
NOTE 1
DMA1
ARM7
78 Mbytes / Sec
DMA1
ARM7
78 Mbytes / Sec
78 Mbytes / Sec
ARM7
DMA1
DMA2
78 Mbytes / Sec
78 Mbytes / Sec
WITH NO CACHE
DMA1
ARM7
ARM7
DMA2
78 Mbytes / Sec
78 Mbytes / Sec
SAME CYCLE WITH CACHE
DMA1
ARM7
78 Mbytes / Sec
DMA1
ARM7
78 Mbytes / Sec
78 Mbytes / Sec
78 Mbytes / Sec
78 Mbytes / Sec
78 Mbytes / Sec
OVER 2 CYCLES EQUATES TO …
78 Mbytes / Sec on DMA
78 Mbytes / Sec with ARM
OVER 2 CYCLES EQUATES TO …
39 Mbytes / Sec 8.5 MIPS
•Assuming SDRAM @ 4-1-1-1 Burst
•CACHE is Single Cycle Memory
•Frequency  44.236MHz
NOTE 1: DMA Context Switch
Time  13 BCLKS
78 Mbytes/Sec 40 MIPS
NET+ARM™ Performance
(X32 SDRAM with 1 DMA Channel)
TYPICAL DESIGN
BUS MASTERING
POTENTIAL BUS MASTERS 
ARM7
4-1-1-1
ARM7
DMA1
78 Mbytes / Sec
11
4-1-1-1
ARM7
DMA1
11
DMA1
DMA1
78 Mbytes / Sec
78 Mbytes / Sec
ARM7
External
11
DMA1
78 Mbytes / Sec
78 Mbytes / Sec
WITH NO CACHE
ARM7
ENI
DMA
EACH BUS MASTER IN THE
CURRENT CYCLE CAN MOVE
4 LONG WORDS… MUST THEN
GIVE UP THE BUS IF ANOTHER BUS
MASTER IS WAITING
ARM7
DMA1
78 Mbytes / Sec
78 Mbytes / Sec
SAME CYCLE WITH CACHE
ARM7
DMA1
78 Mbytes / Sec
ARM7
DMA1
78 Mbytes / Sec
78 Mbytes / Sec
78 Mbytes / Sec
OVER 2 CYCLES EQUATES TO …
78 Mbytes / Sec
78 Mbytes / Sec
78 Mbytes / Sec on DMA
78 Mbytes / Sec with ARM
OVER 2 CYCLES EQUATES TO …
8.8 MIPS
39 Mbytes / Sec
•Assuming SDRAM @ 4-1-1-1 Burst
•CACHE is Single Cycle Memory
•Frequency  44.236MHz
78 Mbytes/Sec 40 MIPS
NET+ARM™ Performance
(X32 SRAM with 1 DMA Channel)
TYPICAL DESIGN
POTENTIAL BUS MASTERS 
ARM7
ARM7
DMA
2-1-1-1
2-1-1-1
DMA
106 Mbytes / Sec
ARM7
ARM7
DMA
106 Mbytes / Sec
106 Mbytes / Sec
WITH NO CACHE
DMA
ENI
DMA
DMA
106 Mbytes / Sec
106 Mbytes / Sec
ARM7
External
EACH BUS MASTER IN THE
CURRENT CYCLE CAN MOVE
4 LONG WORDS… MUST THEN
GIVE UP THE BUS IF ANOTHER BUS
MASTER IS WAITING
ARM7
DMA
106 Mbytes / Sec
106 Mbytes / Sec
SAME CYCLE WITH CACHE
ARM7
DMA
106 Mbytes / Sec
ARM7
DMA
106 Mbytes / Sec
106 Mbytes / Sec
106 Mbytes / Sec
OVER 2 CYCLES EQUATES TO …
106 Mbytes / Sec
106 Mbytes / Sec
106 Mbytes / Sec on DMA
106 Mbytes / Sec with ARM
OVER 2 CYCLES EQUATES TO …
12 MIPS
53 Mbytes / Sec
•Assuming SRAM @ 2-1-1-1 Burst
•CACHE is Single Cycle Memory
•Frequency  44.236MHz
106 Mbytes/Sec 40 MIPS
NET+ARM™ Performance
(X32 SRAM with Multiple DMA Channels)
TYPICAL DESIGN
POTENTIAL BUS MASTERS 
ARM7
DMA
2-1-1-1
2-1-1-1
ENI
EACH BUS MASTER IN THE
CURRENT CYCLE CAN MOVE
4 LONG WORDS… MUST THEN
GIVE UP THE BUS IF ANOTHER BUS
MASTER IS WAITING
External
NOTE 1
DMA1
ARM7
106 Mbytes / Sec
DMA1
106 Mbytes / Sec
106 Mbytes / Sec
WITH NO CACHE
DMA1
ARM7
ARM7
ARM7
106 Mbytes / Sec
106 Mbytes / Sec
DMA1
ARM7
DMA2
ARM7
106 Mbytes / Sec
106 Mbytes / Sec
SAME CYCLE WITH CACHE
DMA1
ARM
106 Mbytes / Sec
DMA1
ARM7
106 Mbytes / Sec
106 Mbytes / Sec
106 Mbytes / Sec
106 Mbytes / Sec
106 Mbytes / Sec
OVER 2 CYCLES EQUATES TO …
106 Mbytes / Sec on DMA
106 Mbytes / Sec with ARM
OVER 2 CYCLES EQUATES TO …
8.5 MIPS
38 Mbytes / Sec
•Assuming SRAM @ 2-1-1-1 Burst
•CACHE is Single Cycle Memory
•Frequency  44.236MHz
NOTE 1: DMA Context Switch
Time  13 BCLKS
106 Mbytes/Sec 40 MIPS
Hardware Overview Summary
• Up to four bus masters: ARM7, DMA, ENI,
External
• Bus master must relinquish the bus to
another waiting master after four long words
transferred
• Cache permits ARM7 to move data
concurrently with DMA
• DMA cannot operate on cached memory
• DMA channel context switch requires 13 clock
cycles