Transcript Interactions of Particles with Matter

ν
Towards Electronics
for a
Long Baseline Neutrino Detector
Alfons Weber
STFC & University of Oxford
Alfons Weber
Dec 2007
Alfons Weber
Issues
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Introduction
State of the Art
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Requirements
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MINOS/OPERA
NOVA
T2K/MINERVA
physics
photo detectors
R&D needs
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Dec 2007
Alfons Weber
Introduction
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There are N Detectors
At least 2N different electronics have been
used to read them out
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No unique solution
Solutions have been adapted from
existing ASICS
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driven by cost, timescale, physics.
not ideal
But get the job done
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Dec 2007
Alfons Weber
Tensions
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Near Detectors
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Far Detectors
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high rate
beam synchronisation
limited channel count
low rate
no beam signal available
huge channel count
Performance
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high dynamic range, precise timestamps
100% lifetime
low cost
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Dec 2007
Alfons Weber
What the following is about
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Electronics, need to integrate with
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Photo-detectors
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PMT, APD, MPPC
DAQ
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DAQ
photo detectors
PCs?
Detector
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scintillator with WLS fibre
large PMT arrays?
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Dec 2007
Alfons Weber
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Solution: MINOS ND
Input
current
Analog
Voltage
QIE
8-bit FADC value
FADC
FIFO
3 bit range code
2 bit CAP-ID code
Every channel in the detector (9240) produces,
every 18.87 nsec:
{FADC, RANGE, CAP-ID}
1.4fC lowest count sensitivity, 16-bit effective
dynamic range
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QIE output voltage
CAP-ID: QIE has 4 copies of current
divider/integrator  4 capacitor IDs
Input charge
Based on existing QIE ASIC
dead-timeless for up to 20 μsec (spill)
Dec 2007
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Solution: MINOS ND (II)
Timing System
8 MASTER crates
44 MINDER crates
Analogue
PMT Pulse
Front End
(MINDER/MENUS)
Readout
(MASTER)
Fast readout of
digital data in
response to trigger
Data Acquisition
PVIC Transfers to PCs
Dec 2007
Alfons Weber
Solution: MINOS FD/OPERA
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MINOS developed an ASIC chip for PMT
readout with IDEAS
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32 channels VA32_HDR11
shaping
amplification
sample & hold
output driver to ADC
Excellent product
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fast shaping 500 nsec
noise < 2 fC
linear> 20 pC
6 ASICs multiplexed
onto 1 ADC
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Dec 2007
Alfons Weber
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Solution: MINOS FD (system)
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• Timing System
Trigger-less DAQ system
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ASIC close to PMT
ADC in VME crate
fast PVIC-bus to PC trigger farm
search for hits correlated in space and time
PMTs
2 1 0
2 1 0
HV
VFB
– Absolute time from GPS
(tabs= 200 nsec)
– optical distribute along
large detector (trel= 4 nsec)
2 1 0
HV
VFB
VFB
VARC
2
VARC
1
VARC
0
VARC
1
VARC
2
VME Readout Crates
ROP
serial
PVIC
Ether.
HV
VFB
2.5 MB/s
DAQ
LAN
ROP
serial
PVIC
Ether.
TRC
3
2
1
0
Optical PVIC Bus
RC
B B B B
R R R R
P P P P
Timestamp Clock
1 sec GPS ticks
antenna
GPS
Timing
Central
unit
Timing System
Timing
PC
DAQ
LAN
DCP
10-100 Kbytes/s
Branch
Readout
Processors
40 Mbytes/s
PVIC Bus
DAQ
LAN
DAQ
LAN
To Persistent Store
To Dispatcher
DAQ
LAN
0
3
15
VARC
0
VME
VME
TRC
2 1 0
HV
Front End Electronics
TP
TP
TP
N
1
0
Trigger
Processors
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Alfons Weber
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Solution: T2K/280m & MINERVA
Spill Structure
4.2µs
4.2µs
4.2µs
2-3.53s
2-3.53s
Bunch Structure
58ns
58ns
540ns
Chip Time Structure
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58ns
540ns
58ns
540ns
integration
58ns
540ns
58ns
540ns
58ns
540ns
reset
8 (15) batches
Separated by 540 (241) nsec
charge integrated in batches
58ns
540ns
58ns
540ns
Dec 2007
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TRIP-t Front-end architecture
preamp
integrate/reset
very simplified –
neglecting features not relevant
to ND280 operation
gain adjust
1,2,3,…8
Qin
analogue pipeline
1pF
3pF
gain = 1 or 4
discriminator
x10
disc. O/P
Vth
reset
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only preamp gain affects signal feeding discriminator
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discriminator threshold Vth
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no fine control (x1 or x4)
common to all channels on chip
analogue bias settings
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gain, Vth, etc.
programmable via serial interface
Dec 2007
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TFB1
Gigabit/
Ethernet
Clk & trg
Clk & trg
SCM
FPN
Gigabit/
Ethernet
Special
trigger
GPS
1Hz/100MHz
SiPM0
SiPM63
TFB47
TPS
RMM0
Clk & trg
Cosmic
trigger
(Acc. RF)
Spill trig & #
Gigabit/
Ethernet
…
…
Power
distribution
CTM
MCM
SiPM63
…
data
Clk & trg
Trigger Primitives
TFB0
SiPM0
…
SiPM63
SiPM0
Solution: T2K (System Overview)
Gigabit/
Ethernet
Acronyms:
TFB:
TRIP-t front-end board
RMM:
r/o merger module
CTM:
global trigger module
MCM:
master clock module
SCM:
slave clock module
TPS:
TRIP-t power supply
FPN:
front-end proc. node (PC)
Dec 2007
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Dec 2007
Alfons Weber
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Solution: NOvA
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Dec 2007
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Common Thread
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Different solutions for near and far
detectors
developed around different existing ASICs
heavy use of FPGAs
huge variation in cost
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$20 - $300 per channel
DAQ and electronics can’t be developed
independently
later solutions move towards commercial
back ends
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Dec 2007
Alfons Weber
Requirements
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high QE photo detectors
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low noise electronics
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limited? 1:1000
Timing
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low readout thresholds  bigger detectors
dynamic range
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bigger detectors  cheaper
O(1nsec)
low trigger threshold
low and high rate environment
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Dec 2007
Alfons Weber
Requirements (II)
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Will take a long time for community to
settle on
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detector
photo detector
requirements
Try to develop multi-purpose ASIC
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test beam
near detector
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external trigger, limited lifetime
far detector
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cheap, scalable, ~100% lifetime, self-triggering
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Dec 2007
Alfons Weber
Ingredients
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ADC
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TDC
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local/global
clock distribution
cheap HV supply
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1 nsec
Trigger
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1:1000
30-1000 V
monitoring
commercial interfaces
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Dec 2007
Alfons Weber
The Pass
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Resume
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Performance is not leading edge
Cost is main driving factor
multi purpose device
Work needed
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requirements capture
design multi-purpose readout system
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Electronics
DAQ
Develop ASIC
develop test system
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Dec 2007
Alfons Weber
Who and Where?
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Who is driving this?
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which community
physicists vs. electronics engineers
Where can the work be done?
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major labs
Universities
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Has to be user driven.
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Many questions, few answers.
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