Transcript EE241 - University of California, Berkeley

Multiple Drain Transistor-Based
FPGA Architectures
Gate
Source
Sidewall
Drain
1
Drain
2
Drew Carlson
Pankaj Kalra
EE241 Class Project
May 9, 2005
1
Multiple Drain Transistors


Goal: Reduce cost per fxn
 Multiplexing + memory in
single cell
Multiple Drain Transistor [1]
 Non-volatile switch
connects/disconnects drains
from channel
 Similar to: Sidewall Flash
Memories [2, 3]



Scalable
Reverse-read
Si3N Q
nit
gate
4
Drain1
S
SiO2
n/n-
n+
D2
P+
Dn
Benefits:
 Forward write/read
 Larger effective widths
S
D
[1] A.Carlson and T.-J. King, Device Research Conf., 2005, to be published.
[2] M. Fukuda et al., IEDM Technical Digest, pp.909-912, 2003.
[3] Y.K. Lee et al., J. Vac. Sci. & Tech. B, 22, pp.2493-2498, 2004.
Carlson / Kalra – MDT-based FPGAs
2
Building a SPICE Model




G
Subcircuit Model
Driving & coupling
MOSFETs
Effective widths from
geometry calculations
Resistive LDDs
Process Model



Square law approach
1-drain MOSFET I-V
curves from MEDICI
(device sim.)
Fit SPICE parameters to
curves
D1
S
D2
350
300
Curves: SPICE
Markers: MEDICI
250
Id (uA/um)

200
150
100
Vgs = 0.6V, 0.8V, 1.0V.
50
0
0.0
Carlson / Kalra – MDT-based FPGAs
0.2
0.4
0.6
0.8
1.0
Vd (V)
3
Field Programmable Gate
Arrays (FPGAs)

Routing Fabric



LUT
DQ
>
6T Switch

Logic Block
Horizontal & vertical
channels meet at switch
blocks
70-90% die area
Limiting Constraint:
Area
 (# switches) x (switch
area)
 Minimize either / both
Logical Blocks

[1] H. Schmit and V. Chandra, “Layout Techniques for FPGA Switch
Blocks,” IEEE Trans. VLSI Systems, vol. 13, pp.96-105, Jan. 2005.
Program to any function
w/ Look Up Table (LUT)
Carlson / Kalra – MDT-based FPGAs
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Smaller Switches
Pass Transistor
SRAM
200
0
0
0
(multiplicity n)
Buffered Switch

400
1000
Savings in fanout (pass)
SRAM
5
Time (ns) 4
150
600
400
200
vs.
2
T ime (ns)
800
Drain Voltage (mV)

600
0
vs.
(n drains)
150
Power (uW)

Up to 7x area reduction
Comparable
performance
Power (uW)

800
Drain Voltage (mV)

1000
0
0 T ime (ns) 40
SRAM
0
0
Carlson / Kalra – MDT-based FPGAs
10
20
T ime (ns)
30
40
5
Smaller Switch Blocks

Disjoint
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Channel Width = 4,
Flexibility = 3,
Wpass=10Wmin
4.37μm x 5.81μm (vs. 124
μm2)

3 MDT / switch
Carlson / Kalra – MDT-based FPGAs
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More Routability

Universal

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Channel Width = 4,
Flexibility = 9, Wpass=10Wmin
17.73μm x 6.57μm (vs. 394 μm2)
Carlson / Kalra – MDT-based FPGAs
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SRAM LUT
S0 .
.
S3
S0
LUT
S1
OUT
SRAM
S2
SRAM
Critical Path
S0
1.4
Voltage (V)
1.0
0.8
Output

0.4
SRAM Data
0.2
0.0
0.0

0.2
0.4
0.6
0.8
Time (ns)
S3
.
.
.
1.2
0.6
.
.
.
1.0
1.2
.
.
.
.
.
.
OUT
Total Area  185 Amin
Delay of critical path = 415ps
Amin (area of minimum width transistor) = 0.324μm2
(90nm process)
Carlson / Kalra – MDT-based FPGAs
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MDT MUX
S0

Pair of double-drain
MDTs and pair of pass
transistors

S1
0
1
Precharge
1
41 MUX
0


41 MUX
Store configuration bits during programming
Reading 0


Output
Select MDT drain pulled to low  Select Pass tx.
Reading 1

Precharge signal pulls output to high
Carlson / Kalra – MDT-based FPGAs
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MDT LUT
S1
S0
Precharge
S2
S3
S0
1.4
.
.
.
.
.
.
Voltage (V)
1.2
Output
1.0
0.8

0.6
0.4

0.2
0.0
0.0
0.5
Data stored
1.0
1.5
Time (ns)
2.0
.
.
.
OUT
Total Area  87 Amin
Delay of critical path = 370ps
53% area reduction
Carlson / Kalra – MDT-based FPGAs
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Programming of MDT
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Programming needs not be very fast (done offline)


Store all the configuration bits in a shift register
Tradeoffs

Charge Pumps to get high voltage level

MDT Programming
Require high voltage pulse
(VG=3V, VD=5V)
 Level-shifter circuit to
generate high-voltage pulse
Level Shifter
Vpp



Vdd
In
Feedback pMOS type
Cross-coupled pMOS type
Carlson / Kalra – MDT-based FPGAs
Out
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Summary

Novel device structure
studied for reconfigurable
applications
MDT based FPGA
architecture is proposed


Routing fabric :
up to 80% area reduction
LUT:
up to 53% area reduction
Normalized Area

1.50
SRAM based
MDT based
1.25
1.00
0.75
0.50
0.25
0.00
Universal Switch Disjoint switch
Carlson / Kalra – MDT-based FPGAs
LUT
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