Transcript Chapter 4

Chapter 4
Introduction to PLDs and
QUARTUS II
Programmable Logic Device
(PLD)
• Supplied with no predetermined logic
function.
• Programmed by user to implement any
digital logic function.
• Requires specialized computer software
for design and programming.
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Advantages of Using PLDs
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Saves on number of chips used.
Saves on different types of chips used.
Shortens the design process.
Creates design flexibility.
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Complex PLD (CPLD)
• A PLD that has several programmable
sections with internal interconnections
between the sections.
• In effect, several interconnected PLDs
on a single chip.
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PLD Programming
• Requires specialized computer software
(e.g., Altera’s Quartus II)
• Programmed through a series of steps
known as the PLD Design Cycle.
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PLD Programming
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PLD Programming
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PLD Design Cycle - 1
• Design entry – enter the circuit design.
• Simulation – verify that the circuit
outputs correctly respond to the inputs.
• Compilation – create the required
design information for programming the
CPLD.
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PLD Design Cycle - 2
• Fitting – determine which portions of
the CPLD to assign as circuitry for the
required design.
• Programming – configures the CPLD
to perform the desired logic function.
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Programmable SOP Array - 1
• Consists of AND gates and OR gates
organized in an SOP array.
• Connections are made or broken by a
matrix of fused links.
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Programmable SOP Array - 2
• Intact fuse connection is made.
• Intact fuse lines are indicated by ‘X’.
• Blown fuse connection is open.
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Programmable SOP Array - 3
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PAL Fuse Matrix & Combinational
Outputs
• Fuse assignments done with special
software.
• The software takes inputs such as
Boolean equations, truth tables, or other
forms.
• Software produces the simplest solution
to the problem.
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PAL Fuse Matrix & Combinational
Outputs
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JEDEC
• Stands for Joint Electron Device
Engineering Council.
• JEDEC file is an industry standard form
of ASCII text file.
• The JEDEC file lists which fuses should
remain intact and which fuses should be
blown.
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Outputs with Programmable
Polarities
• Allows for flexibility in the final design.
• Each output has a programmable XOR
gate associated with the output.
• The XOR gate can be programmed to
act as either an inverter or a buffer.
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Outputs with Programmable
Polarities
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CPLD Development Boards
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Altera UP-2
DeVry eSoc
RSR Electronics PLDT-2
HVW Technologies
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CPLD Development Boards
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Altera’s UP-2 Board
• Contains two target devices:
– MAX7000S family–EPM7128SLC84-7, a
nonvolatile CPLD.
– FLEX10K family–EPF10K70RC240-4, a
volatile CPLD.
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Volatile vs. Nonvolatile
• Volatile–information (programming) is
available only as long as power is
applied to the device.
• Nonvolatile–information (programming)
is available even after power is removed
and then reapplied.
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Quartus II Definitions
• Project–a collection of files associated
with a PLD design.
• Block Diagram File–A design file in
which PLD design information is
entered as a schematic or as a block
diagram.
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Quartus II Design Flow - 1
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Design Entry (Block or Text Editor).
Create Project.
Assign Target Device (PLD).
Compile.
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Quartus II Design Flow - 2
• Simulate (if the simulation produces
errors, make corrections and
recompile).
• Assign input and output pin numbers.
• Recompile.
• Program the target CPLD.
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Quartus II Start-Up Screen
• From the Quartus start-up screen, you
can open all other Quartus applications.
• Toolbar provides shortcuts for frequently
used functions.
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Quartus II Start-Up Screen
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Quartus II Start-Up Screen
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Creating a Block Diagram File
• Select New from the File menu.
• From the dialog box, choose Device
Design Files tab.
• Select Block Diagram/Schematic File.
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Creating a Block Diagram File
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Creating a Block Diagram File
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Creating a New Project - 1
• Must be done before entering any
design information.
• Use the Save As dialog box.
• Enter the file name.
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Creating a New Project - 2
• Save as type Block
Diagram/Schematic File (*.bdf).
• Check the Create new project based
on this file box.
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Creating a New Project - 3
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New Project Wizard - 1
• Allows the user to easily create a new
project and assign some of its basic
settings.
• Helps the user to establish the basic
settings for the project, as well as to add
files and user libraries to, or remove
them from, the project.
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New Project Wizard - 2
• The user can enter:
– Project name and directory.
– Name of the top-level design entity.
– Design files, other source files, and
libraries to be used in the project.
– Device and family to be used.
– EDA tool settings.
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Entering Components
• Open the Edit menu and select Insert
Symbol, or
• Double-click on the Block Editor
desktop.
• Enter the component name in the
Symbol dialog box (e.g., and2).
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Entering Components
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Entering Components
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Aligning Components
• Highlight each component.
• Drag each one to the desired location.
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Aligning Components
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Connecting Components
• Components are connected by clicking
over one end of one component and
dragging a line to one end of a second
component.
• Hovering over a line causes the cursor
to change from an arrow to a cross-hair
with a right angle symbol.
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Connecting Components
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Assigning Pin Names
• Inputs and outputs must be assigned
names.
• Double-click the pin name to highlight
the name.
• Type in the pin name.
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Assigning Pin Names
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Compiling a Design in Quartus II
• Click the Start Compilation button on
the toolbar, or
• Select Start Compilation from the
Processing Menu, or
• Open the Compiler tool from the Tools
menu, and click Start Compilation.
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Compiling a Design in Quartus II
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Compiling a Design in Quartus II
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Compilation Report
• A summary of the compilation.
• More details are available under the
various folders.
• Legal Notice, Flow Setting, etc.
• Folders can be expanded by clicking on
the (+) symbol.
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Compilation Report
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Simulating a Design in Quartus II
• Simulation is based on a Vector
Waveform file (vwf).
• The Vector Waveform file contains
simulation input and output values
defined as graphical waveforms.
• The input and output values are defined
by the designer.
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The Quartus II Simulator
• Performs a functional simulation to test
the logical operation of your design, or
• Performs a timing simulation to test both
the logical operation and the worst-case
timing for the design in the target
device.
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Creating a Vector Waveform File
• Click New from the File menu or select
the appropriate toolbar button.
• In the New File dialog box, select the
Other Files tab.
• Select Vector Waveform File.
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Creating a Vector Waveform File
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Entering Waveforms in the Editor
• Start the Node Finder by clicking on the
toolbar button or by selecting Utility
Windows/Node Finder from the View
menu.
• Click Start to display the list of nodes.
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Entering Waveforms in the Editor
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Entering Waveforms in the Editor
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Adding the Required Nodes
• In the Node Finder, click on the
waveform to highlight it.
• Drag and drop the waveform in place in
the Waveform Editor window.
• Once all waveforms have been added,
Save and Close the Node Finder
window.
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Adding the Required Nodes
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Simulation Time
• Each CPLD has a delay time from input
to output specified in nanoseconds.
• This is indicated by the number at the
end of the CPLD’s part number.
• The simulation time should be long
compared to the input-output delay time
of the CPLD.
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Quartus II Default Time
• In Quartus, the default End Time for a
simulation is set at 100 nS.
• For most applications, this time will
need to be changed.
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Changing the End Time
• Select End Time from the Edit menu.
• In the End Time dialog box, change the
unit from nS (nanoseconds) to S
(microseconds).
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Changing the End Time
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Viewing the Waveform
• The entire waveform can be viewed by
selecting Fit in Window from the View
menu, or
• Using the Zoom In, Zoom Out, and Fit
in Window buttons on the Waveform
Editor toolbar.
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Viewing the Waveform
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Grouping Waveforms – 1
• Waveforms can be entered individually
or as a group of waveforms.
• To highlight a group, click on the top
waveform and then drag the cursor to
the last waveform of the group.
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Grouping Waveforms – 2
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Grouping Waveforms – 3
• Right-click on the selected group of
waveforms and select Group.
• Enter the group name Inputs.
• Select the radix as Binary.
• Click OK.
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Grouping Waveforms – 4
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Grouping Waveforms – 5
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Grouping Waveforms – 6
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Counting Waveform Dialog Tab
• Click on the waveform group Inputs.
• Click the Count Value toolbar button.
• In the Counting tab of the Count Value
dialog box, select
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Radix: Binary
Start value: 000
Increment by: 1
Count type: Binary.
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Counting Waveform Dialog Tab
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Timing Waveform Dialog Tab
• Select
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Start time: 0 ps
End time: 100 S
Count every: 10.24 S
Multiplied by: 1
• Count interval of 10.24 S matches the
spacing of the Waveform Editor timing grid.
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Timing Waveform Dialog Tab
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Timing Waveform Dialog Tab
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Starting the Simulation
• Select Start Simulation from the
toolbar, or
• Select Start Simulation from the
Processing menu.
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Starting the Simulation
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Using the Simulator for
Troubleshooting
• Simulation is a valuable tool that provides the
designer with the means of finding errors in
the design entry of a project.
• Should errors be identified through the
simulation process, they must then be
corrected before programming the design on
a CPLD.
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Using the Simulator for
Troubleshooting
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Using the Simulator for
Troubleshooting
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Transferring a Design to a CPLD
• Assign pin numbers to each assigned
pin name.
• Assign the Device.
• Recompile the file.
• Use the Quartus programming tool to
transfer the design from the PC to the
CPLD.
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Quartus II Assignment Editor – 1
• The Assignment Editor is the interface
for creating and editing node and entity
specific assignments in the Quartus II
software.
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Quartus II Assignment Editor – 2
• Assignments are logic functions you
assign to a physical resource on the
device, or compilation resources you
assign to logic functions.
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Using the Assigning Pins Dialog
Box
• Open the Assign Pins dialog box from
the Assignment menu.
• The Assign Pins dialog box shows a
list of pin numbers available on the
selected device.
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Assigning Pins
• In the Assign Pins dialog box, click the
line showing the pin number.
• Type the pin name of the input or output
in the Pin Name box.
• Click Add.
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Assigning Pins
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Assigning Pins
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Assigning Pins
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Using the Assignment Editor
• Open the Assignment Editor from the
Assignments menu.
• Click the Pin button to see the pin
assignment screen.
• Under the Name column, select a pin
name from the drop-down box.
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Using the Assignment Editor
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Using the Assignment Editor
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Using the Assignment Editor
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Programming the UP-1 or UP-2
Board
• Programming the UP-1 or UP-2 board
requires:
– A ByteBlaster II or Byteblaster MV cable.
– The programming software in Quartus II.
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Programming the UP-1 or UP-2
Board
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ByteBlaster II & ByteBlaster
MV – 1
• Connects to the parallel port of the PC
• Complies with the JTAG (Joint Test
action Group) standard.
• The operation of the JTAG port is
controlled automatically by Quartus II.
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ByteBlaster II & ByteBlaster
MV – 2
• Used to program PLDs connected to a
circuit board (e.g., UP-1 or UP-2).
• In-System Programmable (ISP) – MAX
7000s family.
• In-Circuit-Reconfigurable (ICR) – FLEX
10K family.
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Quartus II Programmer – 1
• Open the Programmer from the toolbar
or from the Tools menu.
• Click the Hardware button.
• In the Hardware Setup dialog box,
click Add Hardware.
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Quartus II Programmer – 2
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Quartus II Programmer – 1
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Quartus II Programmer – 2
• In the Add Hardware dialog box, select
Hardware Type: ByteBlasterMV or
ByteBlasterII.
• Select the port LPT1 (or any available
LPT port).
• Click OK.
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Quartus II Programmer – 3
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Quartus II Programmer – 4
• In the Hardware Setup dialog box,
highlight ByteBlasterMV in the
Available Hardware Items.
• Click Select Hardware.
• Close to return to the Programmer
dialog box.
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Quartus II Programmer – 5
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Quartus II Programmer – 6
• In the Programmer dialog box, highlight
the required programming file.
• Check Program/Configure.
• Click Start Programming.
• Programming progress is shown by the
Progress indicator.
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Quartus II Programmer – 7
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Quartus II Programmer – 8
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Symbol Files
• A file that represents a PLD design as a
graphic symbol.
• Only the inputs and outputs are shown.
• The symbol can be used as a
component in any Block Diagram File.
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Symbol Files
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Creating a Symbol File
• Open the Block Diagram File.
• Select Create/Update from the file menu.
• From the secondary menu, select Create
Symbol Files for Current File.
• A symbol file is created with the same name
as the Block Diagram File, but with extension
.bsf.
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User Libraries
• During compilation, Quartus searches
for a component – first in the project’s
working directory, then in the user
library.
• Before compilation, any new symbol
files that are created must be stored in
the user library.
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Creating a Path to a User
Library – 1
• Create a new Block Diagram File.
• When saving the file, check the box
Create new project based on this file.
• In the Add Files dialog box, click User
Library Pathnames.
• Click the (…) button to browse the
directory tree.
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Creating a Path to a User
Library – 2
• Find the folder containing the applicable
project files.
• Click Open.
• The folder file now will appear in the
Libraries box.
• Click OK.
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Creating a Path to a User
Library – 3
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Hierarchical Designs
• A PLD design ordered in layers or
levels.
• The top level contains components that
are themselves complete designs.
• Lower-level components may have
even lower-level designs embedded
within them.
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Top Level of a Hierarchy
• The file in a hierarchy that contains
components specified in other design files
and is not in itself a component of a higher
level file.
• Quartus II displays the hierarchy of a design
in a window to the left of the workspace called
the Project Navigator Window.
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Top Level of a Hierarchy
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Top Level of a Hierarchy
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Top Level of a Hierarchy
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