Transcript Part 1 Module 6 Analogue Digital Converter

Module 6 : Analogue Digital Converter C28x
32-Bit-Digital Signal Controller
TMS320F2812
Texas Instruments Incorporated
European Customer Training Center
University of Applied Sciences Zwickau (FH)
6-1
ADC Module



12-bit resolution ADC core
Sixteen analog inputs (range of 0 to 3V)
Two analog input multiplexers




Up to 8 analog input channels each
Two sample/hold units (for each input mux)
Sequential and simultaneous sampling modes
Auto sequencing capability - up to 16 auto
conversions

Two independent 8-state sequencers




“Dual-sequencer mode”
“Cascaded mode”
Sixteen individually addressable result registers
Multiple trigger sources for start-of-conversion

External trigger, S/W, and Event Manager events
6-2
ADC Module Block Diagram (Cascaded Mode)
Analog MUX
...
MUX
A
ADCINA7
ADCINB0
ADCINB1
Result MUX
S/H
A
S/H
MUX
...
MUX
B
ADCINB7
S/H
B
RESULT0
RESULT1
12-bit A/D
Converter
SOC
EOC
RESULT2
Result
Select
...
ADCINA0
ADCINA1
RESULT15
Auto sequencer
MAX_CONV1
...
Software
EVA
EVB
Ext Pin (ADCSOC)
CHSEL00 (state 0)
CHSEL01 (state 1)
CHSEL02 (state 2)
CHSEL03 (state 3)
CHSEL15 (state 15)
Start Sequence
Trigger
6-3
ADC Module Block Diagram (Dual-Sequencer mode)
Analog MUX
ADCINA7
ADCINB0
ADCINB1
...
ADCINB7
S/H
MUX
MUX
B
S/H
B
Result
Select
Sequencer
Arbiter
SOC1/
EOC1
SEQ1
Auto sequencer
SEQ2
Auto sequencer
MAX_CONV1
MAX_CONV2
CHSEL00 (state 0)
CHSEL01 (state 1)
CHSEL02 (state 2)
CHSEL08 (state 8)
CHSEL09 (state 9)
CHSEL10 (state 10)
CHSEL07 (state 7)
Start Sequence
Trigger
CHSEL15 (state 15)
Start Sequence
Trigger
RESULT7
RESULT8
RESULT9
SOC2/
EOC2
...
(ADCSOC)
12-bit A/D
Converter
...
Software
EVA
Ext Pin
RESULT0
RESULT1
S/H
A
...
...
MUX
A
Result MUX
Result
Select
...
ADCINA0
ADCINA1
RESULT15
Software
EVB
6-4
F2812 ADC Clocking Example
CLKIN PLLCR
(30 MHz)
DIV
bits
HISPCP
SYSCLKOUT
(150 MHz)
HSPCLK
(150 MHz)
HSPCLK
bits
To CPU
1010b
000b
PCLKCR.ADCENCLK = 1
ADCTRL3
ADCCLKPS
bits
FCLK
(25 MHz)
0011b
FCLK = HSPCLK/(2*ADCCLKPS)
ADCTRL1
CPS bit
0b
ADCCLK =
FCLK/(CPS+1)
ADCCLK
(25 MHz)
ADCTRL1
ACQ_PS
bits
To ADC
pipeline
sampling
window
0111b
sampling window = (ACQ_PS + 1)*(1/ADCCLK)
Important: ADCCLK can be a maximum of 25 MHz!
6-5
Analog-to-Digital Converter Registers
Register
Address
Description
ADCTRL1
0x007100 ADC Control Register 1
ADCTRL2
0x007101 ADC Control Register 2
ADCMAXCONV 0x007102 ADC Maximum Conversion Channels Register
ADCCHSELSEQ1 0x007103 ADC Channel Select Sequencing Control Register 1
ADCCHSELSEQ2 0x007104 ADC Channel Select Sequencing Control Register 2
ADCCHSELSEQ3 0x007105 ADC Channel Select Sequencing Control Register 3
ADCCHSELSEQ4 0x007106 ADC Channel Select Sequencing Control Register 4
ADCASEQSR
0x007107 ADC Auto sequence Status Register
ADCRESULT0
0x007108 ADC Conversion Result Buffer Register 0
ADCRESULT1
0x007109 ADC Conversion Result Buffer Register 1
ADCRESULT2
0x00710A ADC Conversion Result Buffer Register 2
: :
: :
:
:
:
:
:
ADCRESULT14
0x007116 ADC Conversion Result Buffer Register 14
ADCRESULT15
0x007117 ADC Conversion Result Buffer Register 15
ADCTRL3
0x007118 ADC Control Register 3
ADCST
0x007119 ADC Status and Flag Register
6-6
ADC Control Register 1 - Upper Byte
ADCTRL1 @ 0x007100
ADC Module Reset
Acquisition Time Prescale (S/H)
0 = no effect
1 = reset (set back to 0
by ADC logic)
15
14
reserved
RESET
13
Value = (binary+1)
* Time dependent on the “Conversion
Clock Prescale” bit (Bit 7 “CPS”)
12
11
10
9
8
SUSMOD1 SUSMOD0 ACQ_PS3 ACQ_PS2 ACQ_PS1 ACQ_PS0
Emulation Suspend Mode
00 = [Mode 0] free run (do not stop)
01 = [Mode 1] stop after current sequence
10 = [Mode 2] stop after current conversion
11 = [Mode 3] stop immediately
6-7
ADC Control Register 1 - Lower Byte
ADCTRL1 @ 0x007100
Continuous Run
Sequencer Mode
0 = stops after reaching
end of sequence
1 = continuous (starts all over
again from “initial state”)
0 = dual mode
1 = cascaded mode
7
6
CPS
CONT_RUN
Conversion Prescale
0 = CLK / 1
1 = CLK / 2
5
4
3
2
1
0
SEQ1_OVRD SEQ_CASC reserved reserved reserved reserved
Sequencer Override
(continuous run mode)
0 = sequencer pointer resets to “initial state”
at end of MAX_CONVn
1 = sequencer pointer resets to “initial state”
after “end state”
6-8
ADC Control Register 2 - Upper Byte
ADCTRL2 @ 0x007101
EVB SOC
EVA SOC
SEQ1 Mask Bit
(cascaded mode only)
0 = no action
1 = start by EVB
Start Conversion (SEQ1)
signal
0 = clear pending SOC trigger
1 = software trigger-start SEQ1
15
14
13
12
EVB_SOC
RST_SEQ1 SOC_SEQ1 reserved
_SEQ
Reset SEQ1
0 = no action
1 = immediate reset
SEQ1 to “initial state”
11
0 = cannot be started
by EVA trigger
1 = can be started
by EVA trigger
10
INT_ENA_ INT_MOD
SEQ1
_SEQ1
9
8
reserved
EVA_SOC_
SEQ1
Interrupt Enable (SEQ1)
0 = interrupt disable
1 = interrupt enable
Interrupt Mode (SEQ1)
0 = interrupt every EOS
1 = interrupt every other EOS
6-9
ADC Control Register 2 - Lower Byte
ADCTRL2 @ 0x007101
External SOC (SEQ1)
EVB SOC
SEQ2 Mask bit
0 = no action
1 = start by signal
from ADCSOC pin
0 = cannot be started
by EVB trigger
1 = can be started
by EVB trigger
Start Conversion (SEQ2)
(dual-sequencer mode only)
0 = clear pending SOC trigger
1 = software trigger-start SEQ2
7
6
5
4
EXT_SOC
RST_SEQ2 SOC_SEQ2 reserved
_SEQ1
3
2
INT_ENA_ INT_MOD
SEQ2
_SEQ2
Reset SEQ2
Interrupt Enable (SEQ2)
0 = no action
1 = immediate reset
SEQ2 to “initial state”
0 = interrupt disable
1 = interrupt enable
1
0
reserved
EVB_SOC_
SEQ2
Interrupt Mode (SEQ2)
0 = interrupt every EOS
1 = interrupt every other EOS
6 - 10
ADC Control Register 3
ADCTRL3 @ 0x007118
ADC Reference
Power Down
ADC Bandgap
Power Down
ADC Power Down
(except Bandgap & Ref.)
0 = powered down
1 = powered up
0 = powered down
1 = powered up
0 = powered down
1 = powered up
15 - 8
reserved
4
3
7
6
5
ADCRFDN
ADCBGND
ADCPWDN
2
1
0
ADCCLKPS3 ADCCLKPS2 ADCCLKPS1 ADCCLKPS0 SMODE_SEL
ADC Clock Prescale
Sampling Mode Select
0 = sequential sampling mode
1 = simultaneous sampling mode
6 - 11
Maximum Conversion Channels Register
ADCMAXCONV @ 0x007102
 Bit fields define the maximum number of auto conversions (binary+1)
Cascaded Mode
reserved
MAX_
MAX_
MAX_
MAX_
MAX_
MAX_
MAX_
CONV 2_2 CONV 2_1 CONV 2_0 CONV 1_3 CONV 1_2 CONV 1_1 CONV 1_0
SEQ2
Dual Mode
SEQ1
 Auto conversion session always starts with the “initial state”
and continues sequentially until the “end state”, if allowed
Initial state
End state
SEQ1
CONV00
CONV07
SEQ2
CONV08
CONV15
Cascaded
CONV00
CONV15
6 - 12
ADC Input Channel Select Sequencing
Control Register
Bits 15-12
0x007103
0x007104
0x007105
0x007106
Bits 11-8
Bits 7-4
Bits 3-0
CONV03 CONV02 CONV01 CONV00
CONV07 CONV06 CONV05 CONV04
CONV11 CONV10 CONV09 CONV08
CONV15 CONV14 CONV13 CONV12
ADCCHSELSEQ1
ADCCHSELSEQ2
ADCCHSELSEQ3
ADCCHSELSEQ4
6 - 13
Example - Sequencer “Start/Stop” Operation
EVA
Timer 1
EVA
PWM
I1 , I 2 , I3
V1, V2, V3
I1 , I 2 , I3
V 1 , V2 , V3
System Requirements:
•Three auto conversions (I1, I2, I3) off trigger 1 (Timer underflow)
•Three auto conversions (V1, V2, V3) off trigger 2 (Timer period)
Event Manager A (EVA) and SEQ1 are used for this example
with sequential sampling mode
6 - 14
Example - Sequencer “Start/Stop” Operation
(Continued)
• MAX_CONV1 is set to 2 and Channel Select Sequencing Control Registers are set to:
Bits  15-12 11-8 7-4 3-0
0x007103 V1
I3
I2
I1
0x007104
x
x V3 V2
ADCCHSELSEQ1
ADCCHSELSEQ2
• Once reset and initialized, SEQ1 waits for a trigger
• First trigger three conversions performed: CONV00 (I1), CONV01 (I2), CONV02 (I3)
• MAX_CONV1 value is reset to 2 (unless changed by software)
• SEQ1 waits for second trigger
• Second trigger three conversions performed: CONV03 (V1), CONV04 (V2), CONV05 (V3)
• End of second auto conversion session, ADC Results registers have the following values:
RESULT0
RESULT1
RESULT2
I1
I2
I3
RESULT3
RESULT4
RESULT5
V1
V2
V3
 User can reset SEQ1 by software to state CONV00 and repeat same trigger 1, 2 session
• SEQ1 keeps “waiting” at current state for another trigger
6 - 15
ADC Conversion Result Buffer Register
ADCRESULT0 @ 0x007108 through ADCRESULT15 @ 0x007117
(Total of 16 Registers)
15
14
13
12
11
10
9
8
7
6
MSB
5
4
3
2
1
0
LSB
With analog input 0V to 3V, we have:
analog volts
3.0
1.5
0.00073
0
converted value
FFFh
7FFh
1h
0h
RESULTx
1111|1111|1111|0000
0111|1111|1111|0000
0000|0000|0001|0000
0000|0000|0000|0000
6 - 16
How do we Read the Result?
Integer format
x x x x x x x x x x x x 0 0 0 0 RESULTx
bit shift right
15
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x xx x
0
ACC
0 0 0 0 x x x x x x x x x x x x Data Mem
Example: read RESULT0 register
#include "DSP281x_Device.h"
void main(void)
{
Uint16 value;
// unsigned
value = AdcRegs.ADCRESULT0 >> 4;
}
6 - 17
Lab 6: Two Channel Analogue Conversion
initiated by GP Timer 1
AIM :





AD-Conversion of ADCIN_A0 and ADCIN_B0 initiated by
GPT1-period of 0.1 sec.
ADCIN_A0 and ADCIN_B0 are connected to two
potentiometers to control analogue input voltages between 0
and 3,0V.
no GPT1-interrupt-service  Auto-start of ADC with
T1TOADC-bit !!
Use ADC-Interrupt Service Routine to read out the ADC
results
Use main loop to show alternately the two results as lightbeam on LED’s (GPIO port B7..B0)
6 - 18
Additional Registers to initialize Lab 6:
General Purpose Timer Control :
Timer 1 Control
Timer 1 Period
Timer 1 Compare
Timer 1 Counter
Interrupt Flag
Interrupt Enable ask
ADC – Control 3
ADC – Control 2
ADC – Control 1
Channel Select Sequencer 1
Max. number of conversions
ADC - Result 0
ADC - Result 1
:
:
:
:
:
:
:
:
:
:
:
:
:
:
GPTCONA
T1CON
T1PR
T1CMPR
T1CNT
IFR
IER
ADCTRL3
ADCTRL2
ADCTRL1
CHSELSEQ1
MAXCONV
ADCRESULT0
ADCRESULT1
6 - 19
Optional Lab6A
Modify Lab-Exercise 4 ( ‘Knight-Rider’) :
• use the Analogue Input ADCIN0 to change
the frequency for the LED’s
• to add the ADC-setup use Lab6 as a start
• use a LED-frequency range between 50Hz and 1 Hz
• use (1) a linear or (2) a logarithm scale
between Fmin and Fmax.
6 - 20