幻灯片 1 - University of California, Los Angeles

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Transcript 幻灯片 1 - University of California, Los Angeles

PKUnity: A SoC
Design and Verification Platform
Lu Junlin
MicroProcessor R&D Center (MPRC)
Peking University
August 06
Outline
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PKUnity SoC Platform Features
Multi-Layers Verification Framework
CDC Verification Tool
Future Works
August 06
ICDFN 2006
Outline
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PKUnity SoC Platform Features
Multi-Layers Verification Framework
CDC Verification Tool
Future Works
August 06
ICDFN 2006
What for
• Providing a PLATFORM for implementing and
verifying NEW IDEALS in Nanotechnologies
Softwares
Low Power
Compiler
CPU
Synthesis
New Ideas
August 06
RTL Simulation/Emulation
(Verilog/VHDL)
FPGA Prototyping
Network
On-chip
communication
Behavioral Level Simulation
(SystemC)
Multi-Media
Processing
Silicon Proving
PKUnity Platform
ICDFN 2006
What is
• PKUnity Platform includes:
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a scalable and configurable SoC architecture
a series of UniCore CPU
plenty of communication IPs
a verification framework
some verification tools
compilation tool chain and OS based on UniCore
August 06
ICDFN 2006
PKUnity Architecture
UniCore
CPU
Low Speed I/O
and
System Modules
Memory and
High Speed I/O
August 06
ICDFN 2006
Design Features
August 06
ICDFN 2006
Design Features
• CPU
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600MHz UniCore
8-Stage Pipeline
64-bit Floating Point Co-Processor
16KB I/D Cache
2-Port Bus Interface
• Main Memory
– DDR (Double Data Rate) SDRAM
– 166MHz Clock and 64-bit Width
– 2 Memory Access Channels
August 06
ICDFN 2006
Design Features
• High Speed I/O Devices
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10M/100M/1G Ethernet MAC
66MHz PCI Bridge
IDE SATA Controller
USB OTG Controller
• Low Speed I/O Devices
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UART
I2C
SPI
AC’97
PS/2
August 06
ICDFN 2006
Design Flow
Design and
Implementation
RTL Simulation
and Emulation
SystemC-based
FPGA
Prototyping
HW/SW Co-verification
RTL Sign Off
August 06
ICDFN 2006
Challenges
• Gap between CPU and Main Memory
• Different Bus Bandwidth Requirements
• Power Supply
Verification
&
Design
• Complex Communication Protocol
• Lots of Asynchronous Clock Domains
August 06
ICDFN 2006
Design Solutions
• Two-Layer bus
– CPU-MEM bus
– IO-MEM bus
Fast Clock
Best
Performance
CPU-MEM Bus
Minimize
CPU-MEM
bandwidth gap
IO-MEM Bus
August 06
Reduce
the power
supply
Slow Clock
Enough
Performance
ICDFN 2006
Verification Solutions
• Multi-Layer Verification Framework
– For Complex Communication Protocol
• CDC Verification Tool
– For Lots of Asynchronous Clock Domains
August 06
ICDFN 2006
Outline
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PKUnity SoC Platform Features
Multi-Layers Verification Framework
CDC Verification Tool
Future Works
August 06
ICDFN 2006
Verification Challenges
• Complex Communication Protocol
– AHB vs. DDR SDRAM
– AHB vs. PCI
– AHB vs. MAC
– AHB vs. USB OTG
– AHB vs. IDE
– APB vs. AC’97
It’s hard to cover all the
–…
transaction types!
August 06
ICDFN 2006
Verification Methodology
• Multi-Layer
– Signal Layer
– Bus Layer
– Transaction Layer
– Scenario Layer
August 06
ICDFN 2006
Self Checking
• Self Checking by two channels
August 06
ICDFN 2006
Verification Framework
August 06
ICDFN 2006
Example
• Ethernet MAC Verification Coverage
Verification Coverage(2)
100.00
80.00
80.00
Line Coverage
Branch Coverage
Condition Coverage
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60.00
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Module Name
Module Name
Verification Coverage(4)
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Line Coverage
Branch Coverage
Condition Coverage
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Coverage(%)
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Line Coverage
Branch Coverage
Condition Coverage
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Coverage(%)
Verification Coverage(3)
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Line Coverage
Branch Coverage
Condition Coverage
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Coverage(%)
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Coverage(%)
Verification Coverage(1)
Module Name
ICDFN 2006
Outline
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PKUnity SoC Platform Features
Multi-Layers Verification Framework
CDC Verification Tool
Future Works
August 06
ICDFN 2006
What’s CDC
• CDC: Clock Domain Crossing
R1
D
Q
D
FF1
Q
FF2
CLKA
R2
D
Q
R3
FF3
CLKB
CLKA
R1
setup time
hold time
CLKB
CYCLE 1
CYCLE 2
CYCLE 3
metastable
R2
R3
August 06
ICDFN 2006
Challenges
• Lots of Asynchronous Clock Domains
– The relationship of clocks is static in the normal
simulation
– It’s difficult to find setup time and hold time violation
(metastable state)
August 06
ICDFN 2006
Method (Step 1)
1. Find all the CDC paths
– Handshake Logic
– Gray code counter
– ...
ICLK domain
D
HCLK domain
Q
Q
D
D
combination
logic
Q
sample_en
D
Q
Q
D
ram_out[7:0]
FF1
ram_r1
Q
D
EN Q
D
ram_r2
FF4
FF2
FF3
ICLK
ram_out
0x5A
0xA5
HCLK
CYCLE 1
ram_r1
CDC_state
ram_r2
CDC_state
sample_en
CDC_state
Normal
CYCLE 2
CYCLE 3
CYCLE 4
CDC State
Normal
Normal
CDC State
Normal
CYCLE 5
Normal
CDC State
Normal
critical to propagation
August 06
ICDFN 2006
Method (Step 2)
2. Insert a module which can provide
random delays on each CDC paths
4
C
3
B
Clkb
A
Clka
1
2
Clkb
CDC_delay U_RdDMA_D
(.in(RdDMAH), .out(RdDMAH_d));
CDC_delay U_WrDMA_D
(.in(WrDMAH), .out(WrDMAH_d));
Clk_jitter U_ICLK(.in(ICLK), .out(ICLK_j));
CDC_monitor U_RdDMA_M (.in(RdDMAH_d));
CDC_monitor U_WrDMA_M (.in(WrDMAH_d));
always @ (posedge HCLK)
begin
RdDMAH <= (RWCON & !RdDMAH);
WrDMAH <= (!RWCON & !WrDMAH);
end
assign XCS <= !WrDMAH_d & !RdDMAH_d & CS0;
always @ (posedge ICLK_j)
NCS <= (WrReqI | RdReqI) & XCS;
August 06
ICDFN 2006
Method (Step 3)
3. Add reasonable delays on the CDC paths
in simulation repeatedly
Starting Vertex
WrReqH
RdReqH
Observable Vertex
It’s hard to reach
100% coverage,
but it does find some
severe bugs missed in
the normal simulation!
Sequential Logic
@ICLK
@ICLK
Combinational Logic
WrReqI_Meta
RdReqI_Meta
RdDMAH
@ICLK
RdReqI
@ICLK
WrDMAH
!WrDMAH & !RdDMAH & CS
WrReqI
XCS
(WrReqI | RdReqI) & XCS
@ICLK
NCS
August 06
ICDFN 2006
Example
A commercial ATA-5 IDE controller IP
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The table shows coverage
comparability after 30 transactions
finished
The right diagram show the full
coverage growth
70
CDC Coverage (%)
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60
50
40
30
20
10
0
0
1,000
2,000
3,000
4,000
Transaction Num.
5,000
6,000
Table 1: Comparing Code Coverage with CDC Coverage.
Module Name
Function Description
Num.
of Lines
Line
Coverage
Num. of CDC
coverage points
CDC
Coverage
m3s010fa
Asynchronous FIFO
426
97.14%
14336
0.40%
m3s008fa
Asynchronous FIFO Control
917
95.14%
5170
0.39%
m3s007fa
IDE PIO/DMA Timing
Control
353
100%
1458
0.27%
m3s012fa
IDE UDMA Timing Control
470
100%
972
0.41%
m3s005fa
AMBA AHB DMA Control
471
95.70%
620
2.26%
August 06
ICDFN 2006
Outline
•
•
•
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PKUnity SoC Platform Features
Multi-Layers Verification Framework
CDC Verification Tool
Future Works
August 06
ICDFN 2006
Future Works
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Communication Architecture
Bandwidth Allocation Algorithm
CDC Coverage Improvement
…
August 06
ICDFN 2006
Thank You!
August 06
ICDFN 2006