Clock distribution and absolute time calibration in NEMO phase 1

Martino Ruppi INFN di Bari Martino Ruppi – KM3NeT 16 – 18 April 2007 - Pylos

Outlook

• NEMO phase 1 mini-tower • Clock Requirements • Clock Shore Station implementation • Time data flow • The console

Martino Ruppi – KM3NeT 16 – 18 April 2007 - Pylos

NEMO phase 1 mini-tower

PMT16 Floor 4 Floor 3 Floor 2 Floor 1 PMT4 7.5 m Optical Module (OM & FE) PMT1 Junction Box 800 Mbps Synchronous protocol Floor Control Module (FCM) Synchronous protocol PMT15 • • • • FCM Symmetric systems offshore and onshore Dense Wavelength Division Multiplexing (DWDM) based on passive Add&Drop Synchronous Protocol FCM onshore  offshore Recovery clock offshore from data flow DWDM Add&Drop PMT3 PMT2 • • • • • OM Front End (FE) and time stamping in OM Analog signal sampled at fixed rate (200 MHz) Data recording triggered when signal exceeds a remotely-set threshold The clock recovered by FCM is sent to OM Synchronous Protocol FCM  OM

Martino Ruppi – KM3NeT 16 – 18 April 2007 - Pylos

Clock Requirements

Time counting in OMs is based on clock recovered in FCM  Each onshore FCM has to be synchronized by a low-jitter common clock We need to compare the OM time flow with UTC  Onshore clock has to be extracted from GPS clock and time information has to be sent to the apparatus System scaling to KM 3  size The clock produced has to guarantee a very high fan-out

Martino Ruppi – KM3NeT 16 – 18 April 2007 - Pylos

Clock Shore Station

• Recovery clock from GPS receiver • Clock Fan-out toward FCMs onshore • Data and time recovery by IRIG B format • UTC data flow sent to FCMs onshore in synchronous protocol • Go-and-Back time measurements with each pair of onshore/offshore FCM by TDC • Network Time Protocol (NTP) server synchronization of PCs by ethernet NTP GPS Antenna GPS Receiver RS232 PC TDC IRIG B Start x Stop x Connecting Board SCSI Ck 10MHz FPGA • • • • • 4 X LVDS Time Data 4Mbit/s 4 X LVDS Ck 4MHz TDC 25ps sensitive GPS receiver (+/-30 ns RMS) GPS Antenna (now on the roof ot the onshore station) PC control Modular PXI Crate FPGA board National Instr.

Martino Ruppi – KM3NeT 16 – 18 April 2007 - Pylos

Data flow protocol to FCM

UTC start sec.

min hous days Data absolute time Acoustic absolute time frames since 01/01/2006 sec since 01/01/2006 Idle Idle Idle Idle 500 bit = 1/8000 seconds … Idle stop • 8b/10b code (reveling error, scrambling 0/1, byte function embedded) • Time upgraded each 125  • Acoustic data absolute time s • Data (and Slow-Control) absolute time • Room to accomodate more information or commands

Martino Ruppi – KM3NeT 16 – 18 April 2007 - Pylos

The Console (1)

LabView enviroment • FPGA programming Xilinx • PC interface • Instrument remote control • Information storage in DB • Logging • Check alarms • Accessible for control through ethernet

Martino Ruppi – KM3NeT 16 – 18 April 2007 - Pylos

The Console (2)

Off shore time calibration FPGA monitoring and management On shore Time calibration Satellite signal GPS locking Go and Back time measurements TDC Management

Martino Ruppi – KM3NeT 16 – 18 April 2007 - Pylos

Conclusions

• The system is currently working in the NEMO Phase 1 control station • Extension for a full-size 16-floor tower is undergoing (NEMO Phase 2) • The setup can be easily adapted to serve even a KM3-size apparatus (it only needs more modules for the PXI crate)

Martino Ruppi – KM3NeT 16 – 18 April 2007 - Pylos