Transcript Understanding and programming the Host Port Interface

DSP C5000
Chapter 10
Understanding and Programming
the Host Port Interface (EHPI)
Copyright © 2003 Texas Instruments. All rights reserved.
Understanding and Programming the Host
Port Interface (EHPI)
ESIEE, Slide 2
Copyright © 2003 Texas Instruments. All rights reserved.
Understanding and Programming the Host
Port Interface (EHPI)
Copyright © 2003 Texas Instruments. All rights reserved.
C55x EHPI Objectives
 Describe
operation of EHPI
 Understand
the basic setup required to use
the EHPI to perform a task
 Describe
ESIEE, Slide 4
additional capabilities
Copyright © 2003 Texas Instruments. All rights reserved.
CPU/Peripheral Architecture
EHPI allows minimal
EHPI
Hardware glue logic
to connect the C55x
to a standard
5510
CPU
DMA
microprocessor


DARAM
(32KW)
Periph Controller
connects periph
to CPU
SARAM
(128KW)
Serial Ports
Periph protocol
allows maximum
interface speed
PDROM
(16KW)
Timers
External
Memory
GPIO
EMIF
Periph Bus
Controller
ESIEE, Slide 5
Copyright © 2003 Texas Instruments. All rights reserved.
Summary of EHPI Features



ESIEE, Slide 6
The enhanced host port interface
(EHPI) provides a 16-bit-wide parallel
port through which a host processor
(PC, Microcontroller, DSP) can directly
access the memory of the DSP.
The host and the DSP can exchange
information via memory internal or
external to the DSP.
The EHPI uses 23-bit addresses, each
can address a 16-bit word in memory.
Copyright © 2003 Texas Instruments. All rights reserved.
EHPI Features

ACCESS: 16-bit port access to 5510’s internal/external (First 1M x 16)
memory resources

BOOT:
Can boot load DSP’s internal memory during reset

SPEED:
56MBytes/sec @ 200MHz (7 cyc/word, EHPI in “highest” mode)

MODES: Multiplexed Addr/Data, Non-multiplexed (A, D separate)
Host
EHPI
External
Memory
864KW
Internal
Memory
160KW
5510
ESIEE, Slide 7
Let’s see how the EHPI operates...
Copyright © 2003 Texas Instruments. All rights reserved.
EHPI Modes of Operation


The DMA controller handles all EHPI
accesses.
There are two EHPI access configurations:
1) EHPI shares internal memory with the DMA
channels.
2) EHPI has exclusive access to the internal
memory.


ESIEE, Slide 8
The EHPI cannot directly access the
peripherals of the DSP.
Data from or to the peripherals must be
transferred to memory before being
transferred to or from the host.
Copyright © 2003 Texas Instruments. All rights reserved.
EHPI at Reset


ESIEE, Slide 9
At Reset (reset signal low), the EHPI
can access only the internal single-access
RAM (SARAM).
The EHPI can prolong the DSP reset
process so that the host can load code
into the SARAM before the CPU fetches
the DSP reset vector.
Copyright © 2003 Texas Instruments. All rights reserved.
EHPI Modes




ESIEE, Slide 10
EHPI allows two modes for passing data
and addresses to adapt to different
possible hosts:
Non-multiplexed bus to the host
processor is with separate address and
data buses.
Multiplexed mode that provides a single
bus to transport address and data
information.
Each mode requires different
configurations of EHPI signals
Copyright © 2003 Texas Instruments. All rights reserved.
EHPI Registers

EHPI has 3 registers that a host processor can use to
access the memory of the DSP:
1) HPID, EHPI data register a temporary storage for data to
be transferred through the EHPI (Read or write)
2) HPIA , EHPI address register is used in multiplexed mode
to store a 16- or 20-bit address for a read or write operation.
Not used in non multiplexed mode where address is
available through HA[19:0]
3) HPIC, EHPI control register, is used for transfer control
modes


ESIEE, Slide 11
The Host uses HCNTL1 and/or HCNTL0 signal to
indicate which EHPI register it accesses.
The DSP can never access in read or write to these
registers.
Copyright © 2003 Texas Instruments. All rights reserved.
EHPI Control Reset Bit

HPIC register contents defines EHPI
mode of operation:



ESIEE, Slide 12
RESET, bit 0 of HPIC, is cleared when the
DSP reset signal is asserted at the pin, and
remains 0 after the reset signal returns to
the high level. The DSP CPU does not start
running until the host sets the RESET bit.
Then host can access the C55x to download
code to internal SRAM.
When the download is complete, the host
can set the RESET bit to start the CPU
after the reset signal returns to the high
level. The DSP CPU does not start running
until the host sets the RESET bit.
Copyright © 2003 Texas Instruments. All rights reserved.



ESIEE, Slide 13
EHPI Control Host to
DSP Interrupt Request
The host can send a maskable interrupt
request to the DSP CPU by writing a 1
to DSPINT.
If DSPINT bit is 1, the DSP sets the
corresponding flag bit (DSPINT) in IFR
(see Chap 6).
If the DSPINT is enabled, the CPU will
validate the interrupt request and clear
the CPU’s DSPINT otherwise, the CPU
will ignore it.
Copyright © 2003 Texas Instruments. All rights reserved.
Interrupts Between Host and DSP
Interrupt Request from the Host to the DSP
Non-multiplexed mode, HCNTL0 =0
HCNTL0
multiplexed mode , HCNTL1 and HCNTL0=0
HCNTL1
HINT
DSP
Write a 1 to bit DSPINT of HPIC.
Interrupt Request from the DSP to the Host




The DSP can send an interrupt request to the host by
clearing and then setting the HINT bit in status
register ST3_55 of the CPU. This will change the
HINT output.
No acknowledgment path from the host to the HINT
bit.
A space in memory can be shared by the host and the
DSP to create an acknowledgment path to the
interrupt.
During a DSP reset, the CPU sets the HINT bit and
HINT_ goes high (inactive).
ESIEE, Slide 14
Copyright © 2003 Texas Instruments. All rights reserved.
EHPI Control Extended Address Enable bit


ESIEE, Slide 15
XADD, bit 5 of HPIC, is used in
multiplexed mode only and determines
wether values written to HPIA go to
HPIA(15-0) or to HPIA(19-16)
In the multiplexed mode of the EHPI,
the EHPI address register (HPIA) is
loaded via the 16-bit data bus,
HD[15:0]. When a 20-bit address is
used, HPIA must be loaded with two
transfers across HD[15:0] using XADD
control.
Copyright © 2003 Texas Instruments. All rights reserved.
EHPI Signals Non-multiplexed Mode
HD: Data Bus
HA: Adress Bus
HB: Bit Enable
HCS: Chip Select
HR/W: Host Read/Write
HDS1: Data Strobe
HDS2: Data Strobe
HRDY: EHPI Ready
HCNTL0: EHPI Access
HMODE= 1 Non MUX
EHPIENA= 1 Enable EHPI
HINT: DSP to host Interrupt
ESIEE, Slide 16
Copyright © 2003 Texas Instruments. All rights reserved.
EHPI Operation (Non-multiplexed)

Hardware Setup
- Use HMODE to select multiplexed vs. non-multiplexed address/data
- Tie EHPIENA high to use EHPI

Operation
- Host presents HA, HD and control (HCNTL0 picks HPID/HPIC access)
- EHPI sets up DMA to perform access, DMA reads/writes, next access
Host
EHPI
A HA[19:0]
D
Ctrl
HD[15:0]
HPIA
20
DMA
DMA Bus
Control
EHPIENA
HPID
16
Control
HPIC
External
Memory
864KW
Data
HMODE
- multiplexed
- non-multi
ESIEE, Slide 17
Addr
Internal
Memory
What else can
the EHPI do?
160KW
5510
HCNTL0 (accessing HPID or HPIC?)
Copyright © 2003 Texas Instruments. All rights reserved.
EHPI Multiplexed mode
Multiplexed
mode
Use HD[15:0] only,
shared addr/data bus
Data access: write
HPIAddress then
HPIData, autoincrement available.
ESIEE, Slide 18
Copyright © 2003 Texas Instruments. All rights reserved.
Other EHPI Issues
HPIC
5
1
0
XADD
DSPINT
RESET
Fetch RS vector



EHPI Boot Load during Reset
- Set EHPIENA = 1
- Write HPICRESET = 1 when done
Interrupts
- DSP to Host (HINT in ST3)
- Host to DSP (DSPINT in HPIC)
CPU RS
HPI RS
Boot
HPICRESET = 1
Misc Issues
- Byte access: use HBE[1:0]
- If >64K access required, set XADD to enable HA[19:16]
- Fast access? Set EHPI = highest priority in DMA.
- EHPI cannot write to peripheral registers (no access to I/O space)
ESIEE, Slide 19
Copyright © 2003 Texas Instruments. All rights reserved.
C54x EHPI
ESIEE, Slide 20
Copyright © 2003 Texas Instruments. All rights reserved.
C54x EHPI Objectives
 Describe
operation of EHPI
 Understand
the basic setup required to use
the EHPI to perform a task
 Describe
ESIEE, Slide 21
additional capabilities
Copyright © 2003 Texas Instruments. All rights reserved.
Enhanced Host Port Interface (EHPI)

ACCESS: 8/16-bit port access to 54’s on-chip memory resources

BOOT:
Can boot load DSP’s internal memory

SPEED:
33MBytes/sec @ 100MHz (6 cycles/word, max)

MODES: Multiplexed Address/Data, Non-multiplexed (A, D separate)
Host
EHPI
Internal
Memory
ESIEE, Slide 22
Let’s see how the EHPI operates...
Copyright © 2003 Texas Instruments. All rights reserved.
EHPI Operation (Non-multiplexed)

Hardware Setup
- Use HMODE to select multiplexed vs. non-multiplexed address/data
- Tie HPIENA high to use EHPI

Operation
- Host presents HA, HD and control (HCNTL0 picks HPID/HPIC access)
- EHPI sets up DMA to perform access, DMA reads/writes, next access
Host
EHPI
A HA[x:0]
D
Ctrl
HD[y:0]
Addr
HPIA
x
DMA
DMA Bus
Data
Control
HMODE
- multiplexed
- non-multi
HPID
y
Control
HPIC
Internal
Memory
What else can
the EHPI do?
HPIENA
ESIEE, Slide 23
Copyright © 2003 Texas Instruments. All rights reserved.
Other EHPI Issues
ESIEE, Slide 24

EHPI Bootload during Reset (some devices)
- hold device in reset, transfer data, release reset

Full Memory Access
- Host has full access to internal memory

Interrupts
- DSP to Host
- Host to DSP

Multiplexed Address/Data lines (Intel access)
- Uses HD[15/7:0] only, shared address/data bus

EHPI always has priority to DMA bus
Copyright © 2003 Texas Instruments. All rights reserved.
Chip Support Library

CSL exists to simplify the programming of on-chip peripherals.

The library is primarily written in C and organized into discrete
modules with individual APIs. These modules are:
CSL
DAT
CHIP
DMA
EBUS
GPIO
HPI
IRQ
MCBSP
PWR
STDINC
TIMER

ESIEE, Slide 25
Top level module
Device independent data copy/fill
Device specific module
Direct memory access
External memory bus interface
General purpose I/O
Host port interface
Interrupt controller
Multichannel buffered serial port
Power down
Standard include module
Timer module
CSL is configured via the CCS 2.0 BIOS configuration tool
Refer to SPRU480 for complete information
Copyright © 2003 Texas Instruments. All rights reserved.