Transcript Networking for Embedded Systems

Memory
Static RAM
Dynamic RAM
Memory technology types
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Read-Only Memory (ROM)
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Non-volatile storage
ROM, PROM, EPROM, EEPROM
Random Access Memory (RAM)
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Static RAM (SRAM)
Dynamic RAM (DRAM)
ROM types
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OT-PROM (one time programmable)
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Mask ROM
Fuse ROM
PROM
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EPROM
EEPROM
Word Line
Word Line
Word Line
Floating
gate
Bit Line
Bit Line
Mask ROM
Fuse ROM
EPROM
Bit Line
EEPROM
Flash Memory
SRAM
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Hold data without external refresh
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Simplicity : don’t require external refresh circuitry
Speed: SRAM is faster than DRAM
Cost: several times more expensive than DRAMs
Size: take up much more space than DRAMs
Power: consume more power than DRAMs
Word Line
Usage: level 1 or level 2 cache
Bit Line
Bit Line
Bit Line
Word Line
SRAM example: Samsung
1Mx4 High-speed CMOS SRAM
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Fast access time:
8, 10ns (Max)
Low power
dissipation
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Stanby: 5mA
(max)
Operating: 80 mA
(8 ns), 65mA
(10ns)
Timing Diagram
DRAM
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Refresh circuit : storage decay in ms
DRAMs take up much less space, typically
¼ the silicon area of SRAMs or less (one
transistor and a capacitor)
Word Line
Bit Line
DRAM Organization
Long rows to simplify refresh
Two new signals: RAS, CAS
Storage Matrix
Row
Decoders
Row Address Strobe
64 x 64
Column Address Strobe
replace Chip Select
Row Address
A11
. . .
A0
RAS
CAS
WE
Column Address &
Control Signals
Column Latches,
Multiplexers/Demultiplexers
Control
Logic
DOUT
DIN
RAS, CAS Addressing
Even to read 1 bit, an entire 64-bit row is read!
Separate addressing into two cycles: Row Address, Column Address
Saves on package pins, speeds RAM access for sequential bits!
Address
Row Address
Col Address
RAS
Read Cycle
CAS
Valid
Dout
Read Row
Row Address Latched
Read Bit Within Row
Column Address Latched
Tri-state
Outputs
Write cycle timing
Address
(1) Latch Row Address
Read Row
Row Address
Col Address
RAS
CAS
(2) WE low
WE
Din
(3) CAS low: replace data bit
(4) RAS high: write back the modified row
(5) CAS high to complete the memory cycle
Valid
RAM Refresh
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Refresh Frequency:(4ms – 64ms)
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RAS-only Refresh (RAS cycling, no CAS cycling)
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4096 word RAM -- refresh each word once every 4 ms
Assume 120ns memory access cycle
This is one refresh cycle every 976 ns (1 in 8 DRAM accesses)!
But RAM is really organized into 64 rows
This is one refresh cycle every 62.5 ms (1 in 500 DRAM accesses)
Large capacity DRAMs have 256 rows, refresh once every 16 ms
External controller remembers last refreshed row
Some memory chips maintain refresh row pointer
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CAS before RAS refresh: if CAS goes low before RAS, then
refresh
DRAM Technologies
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Conventional DRAM
Fast Page Mode (FPM) DRAM
Extended Data Out (EDO) DRAM
Synchronous DRAM (SDRAM)
Double Data Rate SDRAM (DDR SDRAM)
Direct Rambus DRAM (DRDRAM)
Synchronous-Link DRAM (SLDRAM)
Fast Page Mode (FPM)
DRAM
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Sending the row address just once for many
accesses to memory in locations near each other,
improving access time
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Page mode
Burst mode access
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Memory is not read one byte at a time (32 or 64 bits at
a time)
Several consecutive chunks of memory
“x-y-y-y” for four consecutive accesses
Example: Samsung 1Mx16
FPM DRAM
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Power : 5V or 3.3 V, 450-500 mW
Access time : 50ns, 60ns
EDO DRAM: Samsung
1Mx16bit
Synchronous DRAM
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Tied to the system clock
Burst mode
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System timing : 5-1-1-1
Internal interleaving
New memory standard for modern PCs
Speed
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Access time: 10ns, 12ns,…
MHz rating: 100 MHz, 133MHz
Synchronous DRAM, cont’d
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Latency
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2-clock and 4-clock Circuitry
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SDRAMs are still DRAMs
5-1-1-1 (10ns means the second, third and fourth
access times)
2-clock: 2 different DRAM chips on the module
4-clock: 4 different DRAM chips
Packaging
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Usually comes in DIMM packaging
Buffered and unbuffered, 3.3 V and 5.0V
Samsung 8Mx8bitx4 banks
synchronous DRAM
SDRAM DIMM
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64Mx64 SDRAM DIMM based on 32Mx8, 4
banks 3.3v SDRAMs with SPD
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SPD: serial presence detect chip: speed and design
information about the module
Direct Rambus DRAM
(DRDRAM)
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Direct Rambus channel
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High speed 16-bit bus, 400MHz
Transfers at rising and falling edges,
1.6Gbytes/second
Rambus Inline Memory module (RIMM)
Samsung 256/288Mbit
RDRAM
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512K x 16/18 x 32s banks
Mobile, graphics, and large memory
systems
Low latency
Advanced power management
Synchronous-Link DRAM
(SLDRAM)
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SLDRAM Consortium
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Evolutionary design
64bit bus running at a 200 MHz clock speed
(effective speed of 400 MHz)
3.2 Gbytes/second
Open standard
Comparison of
semiconductor memories
Bit org.
Cell
size
(mm2)
Chip
size
(mm2)
Cell
효율
(%)
Real
Access/
cycle
Write
cycle
Erase
time
64M
DRAM
8Mx8b
8k ref
1.7
211
0.52
38/100
(ns)
100
(ns)
-
85/
(mA)
16M
SRAM
2Mx8b
8.4
226
0.59
14/33
(ns)
14
(ns)
-
70/
(mA)
64M
Flash
4Mx16b
1.7
257
0.42
50/100
(ns)
6.4
(ms)
0.8s
* 0.4 mm design rule
Write
횟수
104~
105
Power
consumption
(Act./Stdby)
30/0.1
(mA)