Transcript Critical Power Slope: Understanding the Runtime Effects of

Critical Power Slope:
Understanding the Runtime Effects of
Frequency Scaling
Akihiko Miyoshi†,Charles Lefurgy‡,
Eric Van Hensbergen ‡, Ram Rajamony ‡,
Raj Rajkumar †
† Real-Time and Multimedia Systems Lab
‡Austin Research Laboratory
Dept. of Electrical and Computer Engineering
Carnegie Mellon University
IBM
The Question
• Operating Points
– [600MHz,6V],
[525MHz,4.2V],[450MHz,2.8V],[375MHz,2V],[300MHz, 1.7V],
[225MHz,1.5V],[150MHz,1.45V]
• Where should I operate (for energy efficiency)?
– Dynamic Voltage Scaling (DVS) algorithms
– Lowest performance without sacrificing user/application
requirement
• Why lowest performance is not always the best
– Even for voltage scaling systems
Energy Efficiency
power
Low frequency
High frequency
...
time
Watts
Watts
Eactive
Eactive
Eidle
t
t
Assumption
• Majority of OS policies assume
Watts
Watts
<
Eactive
Eactive
Eidle
t
• Not always the case!
– When it is not the case?
– How do we determine this?
t
Outline
• Motivation
E
–
flow < Efhigh : not always true
– How do we choose which operating points to use?
•
•
•
•
Measurement results
Analytical model: Critical Power Slope
Analysis on voltage scaling systems
Conclusion
Power Management Techniques
• Provides multiple operating points
– [600MHz,6V],[450MHz,2.8V],[300MHz, 1.7V]…etc
• Three empirical data points
– Frequency Scaling
• PowerPC 405GP
– Clock Throttling
• Pentium with ACPI
– Voltage Scaling
• Strong ARM SA-1100
• Note: We are not making any statement on the
benefits of these techniques!
– These are merely samples which real systems use to
manage power.
Basic Results
• Runtime and frequency
– CPU intensive workload: inverse relationship
• Power and frequency
– Frequency scaling, clock throttling processors
• CPU active: linear relationship
• CPU idle: constant
Power
CPU active
m: slope
CPU idle
Frequency
Energy Consumption
• Compare energy consumption at different
operating points
– Same workload W
– Same amount of time t
power
t
Eactive
Eidle
time
2591J
174.3sec
Energy consumption
(Pentium L1 cache read hit)
Joules
3000
2500
2490J
2000
1500
Extra Idle
System Active
1000
500
0
12
25
37
50
62
75
87
CPU performance (%)
100
Energy consumption
(PPC L1 cache read hit)
136J
66.4sec
162J
200
150
Extra Idle
Others
SDRAM
CPU
Joules 100
50
0
66
133
200
MHz
266
Measurement Results
• Results consistent with different workloads
– Register, L1 cache, memory, disk accesses
– Web server (Pentium)
• Pentium
– Highest frequency always energy efficient
• PowerPC
– Lowest frequency always energy efficient
• Why?
– What happens on voltage scaling systems?
Outline
• Motivation
– Which operating points should we consider?
• Measurement results
– Pentium: highest performance better
– PowerPC: lowest performance better
• Analytical model: Critical Power Slope
• Analysis on voltage scaling systems
• Conclusion
Characterization
• CPU intensive workload W
• Frequency f min
– Assume utilization of system = 1
– Tf min units of time to complete W
– Energy consumed
Ef min  Tf min Pf min
• At frequency f ( f
min
)
f min
– Time to compute W: Tf min f
– Remaining extra idle time: Tf min( 1 
Ef  (Tf min
f min
f
) Pf  Tf min (1 
f min
f
f min
f )
) Pidle
Critical Power Slope
Pf  Pf min  m( f  f
min
)
– Power increases linearly with frequency
– m: slope
Ef  (T
f min
f min f
)[ Pf min  m( f  f
min
• Is f min energy efficient??
– True if Ef  Ef min
– Depends on m
)]  Tf min (1 
f min
f
) Pidle
Critical Power Slope cont’d
• Use slope m to characterize system
– Find hypothetical m for Ef
Critical Power Slope (CPS)
mcritical 
 Ef min
and call it
Pf min  Pidle
f min
What does it mean?
m  mcritical
Power
mcritical
mcritical 
Pf min  Pidle
f min
m  mcritical
Pf min
Pidle
Pidle
f min
Freq
• If
Implications of CPS
m  mcritical
– Energy efficient to run at higher freq.
– Pentium
< Ef min
Ef 
W 12W
mcritical  84815MHz
12.5%  .028
W 15W
m  84830MHz
12.5%  .020
• If
m  mcritical
– Energy efficient to run at lower freq.
– PowerPC
Ef  Ef min
2.02W
mcritical  2.2766WMHz
 .0038
3.13W 2.27W
m  266
MHz66 MHz  .0043
Voltage Scaling Processors (Strong Arm SA-1100)
J.Pouwelse, K.Langendoen, and H. Sips, “Dynamic Voltage Scaling on a Low-Power Microprocessor”, MOBICOM2001
CPS for voltage scaling system
• Look at every operating point at frequency
m 
m m
fx
critical
• If
fx
Pfx  Pidlefx
fx
fx
critical
– Energy efficient at higher frequency than fx
• If
m m
fx
fx
critical
– Energy efficient at lower frequency than fx
fx
Analysis on SA-1100
• Above 74MHz
m m
fx
critical
• At 74MHz
74 MHz
critical
74 MHz
m
m
• Below 74MHz
fx
 46 mW
 121mW
 0.001
74 MHz
mW 106 mW
 121
74 MHz59 MHz  0.001
m m
fx
fx
critical
• Energy Inefficient below 74MHz!
Summary
Power
Pentium
Power
Frequency
Power
SA-1100
Frequency
PowerPC
Frequency
CPS: Characterizes the
runtime trade-off of
power management
techniques
Conclusion
• Which operating points should we consider?
– Traditional DVS algorithms attempt to go to lowest
frequency
– Not always the best choice
• Critical Power Slope
• Identifies energy inefficient operating points
• Can be used to inform OS (DVS algorithms) of operating
points it should not consider