Transcript Document

Interrupt driven I/O
MIPS RISC Exception
Mechanism
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The processor operates in
user mode
 kernel mode
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Access to additional set of registers and to usermode restricted memory space available when
the processor operates in kernel mode.
The MIPS RISC architecture includes the notion
of co-processors. If the floating point co-processor
is not present it can be emulated by a software.
Co-processors
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The co-processor C1 execute floating point instructions
and contain floating point registers.
If the coprocessor C1 does not exist and an instruction
specifies a floating point register, a trap occurs. The
exception handler can identify the operation specified and
may invoke software routines to achieve the effect of the
specified operation.
The co-processor C0 is always present and contains
registers useful for handling exceptions but is not
accessible in user mode. C0 includes the status register,
cause register, BadVaddr, and EPC (exception program
counter).
Co-processor 0
name
BadVaddr
Status
Cause
EPC
number
8
12
13
14
information
memory address at which address
exception occurred
interrupt mask and enable bits
exception type and pending interrupts
address of instruction that caused
exception
Cause Register
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The cause register contains information about pending
interrupts and the kinds of exception that occurs.
The contents of the cause register can be copied into an
ordinary register and have the individual bits tested to
determine what caused an exception to occur.
mfc0 $26, $13
The above instruction moves data from coprocessor 0
register $13(cause register) to general purpose register $26
Cause Register
15
pending interrupts
exception code
0
4
5
6
7
12
15
8
6
2 1 0
exception code
meaning
interrupt
load from illegal address
store to illegal address
bus error on instruction fetch
bus error on data reference
arithmetic overflow
floating point exception
Status Register
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The status register contains information about the
status of features of the computer that can be set
by the processor while in kernel mode
indicates whether the
processor was in kernel or
user mode when the last
exception occurred
indicates whether
current status is kernel or user
Status Register
9
8
7
6
5
4
3
2
1
0
Mode
Enable
Mode
Enable
Mode
Enable
15 14 13 12 11 10
Old Prev Cur
Mode: 1=user, 0=kernel
Enable: 1=on, 0=off
EPC (exception program
counter)
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Contains the address of the instruction that was
executing when the exception was generated.
Control can be made to return to this location
to continue the program.
The contents of EPC can be transferred to a
general register via the following instruction
mfc0 Rt, $14
Exception Handler
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The MIPS R32 architecture fixes the starting address of the
exception handler to 0x8000 0180.
A jump table consists of a list of procedure addresses to be
called to deal with the various exception conditions.
In an interrupt, the PC had already been incremented and
EPC would contain the correct return address.
In a syscall, the EPC contains the address of the syscall
itself, thus the exception handler must first increment the
return address by one before the return.
Handling an exception
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An exception has occurred. What happens?
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The hardware
copies PC into EPC ($14 on cop0) and puts correct code
into Cause Reg ($13 on cop0)
 Sets PC to 0x80000180, process
 enters kernel mode
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Exception handler (software)
Checks cause register (bits 5 to 2 of $13 in cp0)
 jumps to exception service routine for the current
exception
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OS Issues
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When an interrupt is serviced the processor must be able to
execute without being interrupted. It must have the capability
of temporarily disabling the interrupt atomically.
If an interrupt occurs while an interrupt service is ongoing, it
is simply deferred and considered a pending interrupt. It is
serviced after the current request terminates.
The MIPS RISC architecture does not allow user programs to
access beyond 0x8000 0000 (the upper half of the
memory). The exception handler is in this part of memory
and only executed in kernel mode.
OS Issues
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Changing the mode back to the mode before the
exception occurs is accomplished via the
instruction eret
Old  Previous  Current
The mode information is stored in the Status
Register and can only be written in the kernel
mode. It can be read in user mode.
OS Issues
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Enabling and disabling of interrupts can be
done either by applying an interrupt mask (IPM)
to bits 10-15, or the enable bit of the Status
Register.
The execution of eret enables interrupts
OS Issues
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A reentrant exception handler is written such
that it is itself interruptible.
Interrupts and traps are assigned priorities.
A check is made for pending interrupt requests
after every instruction.
If there is a pending interrupt request, the
priority is checked. If it has a higher priority
than the currently running code, it serviced first,
otherwise it is ignored.
Enabling interrupts
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By default, interrupts are disabled in SPIM
To use respond to interrupts, a program must
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Enable interrupts
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Enable the interrupt for the specific device
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Status register
Status register
Instruction the device controller to cause interrupts
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Device control memory mapped address
Software: Interrupt Driven
I/O
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Exceptions come in two varieties
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Interrupts are generated by hardware
I/O device
 Clock
 Power down
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Traps are generated by code execution
Division by zero
 Illegal memory address
 System call
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Interrupt driven I/O structure
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Our programs have all run
in kernel mode only
Code to service an
interrupt must be called
from location 0x8000180
We must return to the
address at which the
interrupt occurred
0xffffffff
kernel
0x80000080
0x80000000
stack
0x10000000
0x00400000
0x00000000
code
Interrupt driven I/O structure
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A queue is needed for both input and output
Input
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Characters are added when a keyboard interrupt occurs
Characters are removed when the input function is
called
Output
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Characters are removed when a display interrupt occurs
Characters are added when a keyboard interrupt occurs
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Echoing
Characters are added when the output function is called
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The output function must initiate the first display handler call
Thereafter, interrupts occur when the display becomes ready
Interrupt driven I/O structure
input function
(syscall 8)
User
data
output function
(syscall 4)
input
echo
output
Protecting the buffers
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The input and output buffers may be modified
in response to an interrupt
This could occur while the CPU is in the middle
of executing user code which reads from the
input buffer or writes to the output buffer
To prevent this destructive concurrent access,
we must disable interrupt while accessing the
buffers
Explicitly and status with 0xfffffffe
 Implement I/O functions as system calls
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