Transcript Document

CPU Structure and Function
Arithmetic Logic Unit
Control Unit
Control Registers
Datapath
(Stalling, Chapter 12)
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
Arithmetic Logic Unit
(ALU)
Complementor
 Adder
 Shifter


Control logic


Hardwired/Microprogram
Temporary storage
General purpose registers
 Specialized purpose registers

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 ALU

Actual computation or
processing data
 Control

logic
Control movement of
data and instructions
into and out of CPU
 Registers


General & Special
Purpose
Storage location for
intermediate data
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 Internal
CPU bus to transfer data between
registers and ALU
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 Registers
form the highest level of the memory
hierarchy.


Small set of high speed storage locations
Temporary storage for data and control information
 Two


types of registers:
User-visible (General purpose)
May be referenced by assembly-level instructions
and are thus “visible” to the user.
Control and status registers (Special purpose)
Used to control the operation of the CPU.
Most are not visible to the user.
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
General purpose registers
Can be assigned to a variety of functions.
 Defined to the operations within the instructions.
 Can be used for addressing functions


Data registers
Hold data and cannot be used in the calculation of an
operand address.
 Example accumulator


Address registers
Hold address information.
 Examples: general purpose address registers, segment
pointers, stack pointers, index registers.

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 Condition
codes or Flags

Bits set by the processor hardware as a result of
operations

Can be accessed by a program but not changed
directly

Examples:




sign flag
zero flag
overflow flag
Bit values are used as the basis for conditional jump
instructions.
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 The
ALU has a number of status flags that reflect
the outcome of arithmetic (and bitwise) operations

based on the contents of the destination operand
 Essential






flags:
Zero flag : set when destination equals zero
Sign flag : set when destination is negative
Carry flag : set when unsigned value is out of range
Overflow flag : set when signed value is out of range
Auxillary flag : set when there is carry from lower
nibble to higher nibble in the lower byte
Parity flag : set when there are odd or even number of
1’s in the lower byte
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 Assuming
that the system uses even parity
 The following operation:
06 h
00000110
+ 54 h
01010100
5A h =>
01011010
Carry flag: 0
Sign flag: 0
Auxiliary carry flag: 0 Parity flag: 1
Zero flag: 0
Overflow flag: 0
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2FH + DEH
0010 1111
+ 1101 1110
-------------------1 0000 1101
OF =0, CF = 1, PF = 1, AF = 1, ZF = 0, SF = 0
5432H + 7098H
0101 0100 0011 0011
+ 0111 0000 1001 1000
-------------------------------1100 0100 1100 1011
OF =1, CF = 0, PF = 0, AF = 0, ZF = 0, SF = 1
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3CH – 28H
0011 1100
+ 1101 1000 Two’s complement for 28H
-----------------1 0001 0100
OF =0, CF = 1, PF = 0, AF = 1, ZF = 0, SF = 0
5AH – 7FH
0101 1010
+ 1000 0001 Two’s complement for 7FH
------------------1101 1011
OF =0, CF = 0, PF = 0, AF = 0, ZF = 0, SF = 1
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 General
purpose registers maximize flexibility in
instruction design.
 Special
purpose registers permit implicit
register specification in instructions – reduces
register field size in an instruction.
 No
clear “best” design approach.
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 More
registers permit more operands to be held
within the CPU -- reducing memory bandwidth
requirements to some extent.
 More
registers cause an increase in the field
sizes needed to specify registers in an
instruction word.
 Most
machines use 8-32 registers.
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 Address
registers should be wide enough to hold
the longest address!
 Data
registers should be wide enough to hold
most data types.
 Would
not want to use 64-bit registers if the
vast majority of data operations used 16 and 32bit operands.
 Related
to width of memory data bus.
 Concatenate
formats.
registers together to store longer
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 Registers
that are used during fetching,
decoding and execution of instructions
 Many
are not visible to the user/programmer
 Some
are visible but can not be (easily)
modified
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Registers
Functions
Program counter (PC)/
Instruction pointer (IP)
Points to the next instruction to be
executed.
Instruction register (IR)
Contains the instruction being executed.
Memory address register
(MAR)
Contains the address of the next
memory access.
Memory data/buffer
register (MBR)
Contains the current data fetched from
memory.
Program status word(s)
(PSW/EFLAGS/FLAGS flags)
Superset of condition code register.
Interrupt masks, supervisory modes, etc.
Status information.
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 Consist
of functional units
Arithmetic operations: +, -, *, /
 Boolean operations: OR, AND, NOT, ExOR
 Comparision operations: <, >, =…
 Co-processor for mathematical operations, floating point
operations

 RISC

(Reduced Instruction Set Computers)
Have more than one functional units
 Functional
units can also be implemented using
pipeline architecture (pipeline concept will be discussed
later).
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Control Unit
PSW/EFLAGS/FLAGS
ALU
Registers
Registers
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 We
have learnt that instructions are executed
sequentially.
 The process of the execution of an instruction
consists of several steps which is referred to as
instruction cycle.
 Each step in the instruction cycle consists of several
sequence smaller steps known as micro-operation.
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Flow of data and information between registers during the
instruction cycle varies from processor to processor.
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 Fetch
the instruction
 Decode it
Fetch Cycle
 Fetch operands, if required
 Perform the operation
Execute Cycle
 Store results, if required
 Recognize pending interrupts
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 Every
step of the instruction cycle consist of
micro-operation(s) that are executed at
specified time.
 Every micro-operations is activated and control
based on the signals from the control unit.
 Example of micro-operations:


Transferring data from one register to another
Activating the functional unit of ALU
 Conventional
format using register transfer
language (RTL)

Example: IP/PC  IP/PC +1
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4
registers are involved: IP/PC, MAR, MBR and IR
 The fetch cycle can be written symbolically
using RTL as
t1: MAR  IP/PC
t2: MBR  [MAR];
IP/PC  IP/PC + 1
t3: IR  MBR
t1, t2, t3 is the timing sequence
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


t1: Content of IP/PC that points to the next address of the
instruction to be executed is loaded to MAR and transferred to
memory on the address bus. Next, CU will activate the read
signal of the memory.
t2: Instruction is accessed from the memory and transfer to
CPU on the data bus. This instruction will be loaded into MBR.
At the same time, IP/PC will be incremented so as to point to
the next instruction to be executed.
t3: Instruction in MBR is loaded into IR. The opcode of the
instruction will be decoded and translated so as to determine
the micro-operations for the particular instruction.
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 Proper

sequence must be followed
MAR <- (IP/PC) must precede MBR <- (memory)
 Conflicts


Must not read & write same register at same time
MBR <- (memory) & IR <- (MBR) must not be in same
cycle
 Also:


must be avoided
IP/PC <- (IP/PC)+1 involves addition
Use ALU
May need additional micro-operations
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 Involve
with fetching data from memory before
initiating the execute cycle.
 Example: ADD AX, [2400]
 In this cycle, the operand bits of the instruction
that is in IR are transferred to MAR. The read
control line is activated and the data associated
with the address will be read and transfer to MBR.
t1 : MAR  IR [operand/address]
t2 : MBR  Mem[MAR]
t3: IR[operand]  MBR
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
The opcode of the instruction in IR will be decoded and
related control signals will be generated.
Type of opcode
Operation
Processor-memory
data transfer between CPU and main memory
Processor I/O
Data transfer between CPU and I/O module
Data processing
Some arithmetic or logical operation on data
Control
Alteration of sequence of operations e.g. jump
Combination of above
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 ADD
AX, BX
CU will generate signal to ALU (adder) for the
addition of the content of two registers, AX and
BX and store the result in AX.
 JMP NEXT
(branch to the instruction at location NEXT )
CU will activate the path from MBR to MAR for
the transfer of the address in the operand field
(of the current instruction in IR) to fetch the
next instruction.
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Opcode:
1 – LOAD
5 – ADD
2 - STORE
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1.
2.
3.
4.
5.
6.
The PC contains 300, the address of the first
instruction. This instruction (the value 1940 in
hexadecimal) is loaded into the instruction register IT
and the PC is incremented.
The first 4 bits in the IR indicate that the AC is to be
loaded. The remaining 12 bits specify the address (940)
from which data are to be loaded.
The next instruction (5941) is fetched from location
301 and the PC is incremented.
The old contents of the AC and the contents of location
941 are added and the result is stored in the AC.
The next instruction (2941) is fetched from location
302 and the PC is incremented.
The contents of the AC are stored in location 941.
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Fetch Cycle
Address
Bus
CU
MBR
IR
Control
Bus
Memory
MAR
IP/PC
Data
Bus
AX
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Clock
t0
t1
t2
IP/PC
100
100
101
MAR
100
100
MBR
4450
IR
-
AX
-
t3
101
100
4450
4450
-
t4
t5
101
101
450
450
4450
000A
4450
4450
-
t6
101
450
000A
4450
000A
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µoperation
IP/PC= 100
fetch cycle: MAR  IP/PC;
MBR  [MAR];
IP/PC  IP/PC +1;
IR  MBR
indirect cycle:
MAR IR[operand/address];
MBR  Mem[MAR];
execution cycle:
AX  MBR;
Control
bus
IP/PC
0100
1
MAR
0100
Address
bus
2
MOV AX, N
0100
0101
N = FF
CU
4
MBR
IR
MOV AX, N
3
Data
bus
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0102
0103
Control
bus
IP/PC
0101
MAR
Address
bus
2
0103
MOV AX, N
0100
0101
1
N
N=FF
CU
MBR
IR
FF
MOV AX, N
3
Data
bus
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0102
0103
Steps
IP/PC
Starting Value
0100
MAR
MBR
IR
AX
Fetch Cycle:
MAR IP/PC
0100
Mov AX, N
MBR [MAR]
IP/PC IP/PC + 1
0101
Mov AX, N
IR MBR
Indirect Cycle:
MAR IR[operand/address]
[N]= 0103
MBR  Mem[MAR]
N=FF
Execution Cycle
AX  MBR
N=FF
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

The mechanism by which other system modules may interrupt the
normal processing of the CPU.
These devices are 1-10 orders of magnitude slower than the CPU



CPU can waste vast amounts of processing cycles waiting for these slow
devices to perform their tasks
Interrupts let the CPU execute its normal instruction sequence and
pause to service the external devices only when they signal (the
interrupts) that they are ready for the CPU’s attention.
The processor and the O/S are responsible for recognizing an
interrupt, suspending the user program, servicing the interrupt, and
then resuming the user program.
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

Mechanism by which other modules (e.g. I/O) may
interrupt normal sequence of processing
Program


Timer



Generated by internal processor timer
Used in pre-emptive multi-tasking
I/O


e.g. overflow, division by zero
from I/O controller
Hardware failure

e.g. memory parity error
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 Interrupts
are processed in an interrupt cycle within
the overall instruction cycle.
 At the end of an instruction cycle (operand storage
step), check to see if any interrupts are pending.
 If there aren’t any, proceed with the next
instruction.
 If there are, then:
Suspend execution of the program and save its “state”.
 Jump to the interrupt service routine (ISR) and resume the “normal”
instruction cycle.
 When the ISR is completed, restore the state of the program and resume
its operation.

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 Disable



Processor will ignore further interrupts whilst
processing one interrupt
Interrupts remain pending and are checked after
first interrupt has been processed
Interrupts handled in sequence as they occur
 Define


interrupts
priorities
Low priority interrupts can be interrupted by higher
priority interrupts
When higher priority interrupt has been processed,
processor returns to previous interrupt
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