Transcript Secrets of the DCM: Part 1 - Prevailing Technology, Inc.

Secrets of the
DCM: Part 2
Steven Knapp
General Products Division
([email protected])
NOTICE:
This is an early draft of this presentation.
Please visit the Xilinx Sales Partner Web
(SPW) for the latest version.
http://www.partner.xilinx.com/common/spartan3/faeconf.htm
© 2004 by Xilinx, Inc. All rights reserved.
(v1.2, 11-OCT-2004)
Continuing On …
• This is a continuation of Secrets of the DCM:
Part 1 that covered the following topics …
–
–
–
–
Overview of the DCM and its applications
Basic Delay Locked-Loop (DLL) operation
Clock Wizard
Clock Jitter
Secrets of the DCM (Part I) 2
Workshop Objectives
By the end of this class, you will …
•
•
•
•
•
Understand how the DCM can phase shift clocks
Understand how to generate other clock frequencies
Learn how to build high-speed data interfaces
Overcome various DCM limitations
Legitimately say “DCMs Don’t Confuse Me”
Secrets of the DCM (Part I) 3
Lesson Four
Phase Shifting
DCM Block Diagram
Delay-Locked Loop (DLL)
Output Stage
Delay Taps
CLKFB
Input Stage
CLKIN
DCM
Digital
Frequency
Synthesizer
PSEN
PSINCDEC
PSCLK
RST
Secrets of the DCM (Part I) 5
Phase Shifter (PS)
Status Logic
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
CLKFX180
PSDONE
STATUS[7:0]
LOCKED
Phase Shifting
• The DCM provides various phase shifting options
• Dedicated phase shift outputs
– These signals always maintain their relationship
– Quadrant: CLK0, CLK90, CLK180, CLK270
– Half-Period: CLK2X/CLK2X180, CLKFX/CLKFX180
• Fixed or Variable phase shifting
– Adjust the phase relationship of all DCM clock outputs
– Requires the DCM’s DLL function
Secrets of the DCM (Part I) 6
Quadrant Phase Shifts
Delay (fraction of
clock period)
Phase Shift (degrees)
0
¼T
0°
90°
½T
¾T
1T
180° 270° 360°
CLK0
CLK90
CLK180
CLK270
Clock Period (T)
• CLK90 and CLK270 only available in low-frequency mode
Secrets of the DCM (Part I) 7
Half-Period Phase Shift
Delay (fraction of
clock period)
Phase Shift(degrees)
0
½T
1T
0°
180°
360°
CLK0
CLK180
• CLK2X/CLK2X180
and
CLKFX/CLKFX180
are similar
Clock Period(T)
• Highly useful for high-performance Dual-Data Rate (DDR)
applications
• Guarantees precise half-period timing
Secrets of the DCM (Part I) 8
DDR Example
“Local inversion”
Clock Inversion at I/O Block
Introduces Duty-cycle Distortion
BUFG
CLKIN CLKx
Precise Timing with
Half-Period Phase Shifting
OFDDRCPE
OFDDRCPE
D0
D0
Q
D1
DCM
“Complementary”
CE
C0
C1
D1
DCM
BUFG
CLKIN CLKx
CLKx180
CE
C0
C1
BUFG
CLKx
CLKx
(50% duty cycle)
(50% duty cycle)
Duty-cycle distortion
CLKx at Flip-Flop
CLKx at Flip-Flop
(with duty-cycle distortion)
(with duty-cycle distortion)
180°
Phase Shift
Factor in distortion
when using a single,
inverted clock.
< 150 MHz
Secrets of the DCM (Part I) 9
CLKx180 at Flip-Flop
(with duty-cycle distortion)
≥ 150 MHz
Q
Review: The DLL
Negative Phase Shift
Positive Phase Shift
Clock
Feedback
Delay Line
Clock
Feedback
Phase
Detector
• DLL shifts the feedback until the Clock and the Feedback are in
phase (0° phase shift)
• DLL controls the phase relationship, can be other than 0°
Secrets of the DCM (Part I) 10
Fixed Phase Shifting
CLKIN
Clock Outputs
Fixed Phase Shift
– Limit
The PHASE_SHIFT attribute determines
the initial phase shift position. DCM
initially asserts LOCKED with this phase
shift value. DCM returns to this value
upon RESET.
Fixed Phase Shift
+ Limit
0
Choose
FIXED
Clock Wizard
Phase Shift
FIXED
Type: NONE
Value:
23
2.695 ns 32.344 Degrees
Enter the Fixed
phase shift value
Resulting fixed phase
shift in nanoseconds and
degrees of phase shift
• Fixed phase shift value set during configuration, unchangeable
• Affects all DCM clock outputs
Secrets of the DCM (Part I) 11
Checking If You’re Awake
• A DCM has a FIXED phase shift of 10°
• What is the phase relationship between CLK0 and
CLK90?
Always 90°
• What is the phase relationship between CLKIN and
CLK0?
10° = 0°+ 10°
• What is the phase relationship between CLKIN and
CLK90?
100° = 90°+ 10°
Secrets of the DCM (Part I) 12
Delay Line and Frequency
LIMIT
Clock
Delay Line
Clock
Feedback
Phase
Detector
• Delay line has 255 taps, each 30 ps to 60 ps
• Maximum guaranteed delay line is 10 ns, ~40 ps per tap
• Clock inputs above 100 MHz can be shifted a full period (360°)
– Shift resolution defined by individual tap delay
Secrets of the DCM (Part I) 13
Shift Limits < 100 MHz
BEYOND
LIMIT
Clock
Delay Line
Clock
Feedback
Phase
Detector
• Clock inputs < 100 MHz have clock period longer than
the guaranteed tap length (> 10 ns)
• Can only shift the clock a fraction of the clock period
(<360°)
Secrets of the DCM (Part I) 14
Phase-Shift Limits
• FINE_SHIFT_RANGE = Guaranteed length of delay line = 10 ns
(per data sheet)
• TCLKIN = Period of CLKIN input clock
• TCLKIN > FINE_SHIFT_RANGE (Frequency < 100 MHz)
PHASE_SHIF TLIMITS

  INTEGER


FINE_SHIFT _RANGE 
 256 

T
CLKIN


• TCLKIN ≤ FINE_SHIFT_RANGE (Frequency > 100 MHz)
PHASE_SHIF TLIMITS  255
Secrets of the DCM (Part I) 15
Variable Phase Shifting
CLKIN
Clock Outputs
Fixed Phase Shift
+ Limit
The PHASE_SHIFTattribute determines
the initial phase shift position. DCM
initially asserts LOCKED with this phase
shift value. DCM returns to this value
upon RESET.
Fixed Phase Shift
+ Limit
0
Dynamic Phase Shift
- Limit
Decrement Phase
Shift Value
Enable
Increment/Decrement
Phase Shift Clock
0
Dynamic Phase Shift
+ Limit
DCM Variable Phase
Shift Control
Increment Phase
Shift Value
PSEN
PSINCDEC
PSCLK
PSDONE
STATUS[0]
Phase Shift Done
Variable Phase
Shift Overflow
After the DCM asserts LOCKED, the FPGA
application can increment or decrement the
present phase shift value using the Dynamic
Phase Shift Control logic.
Secrets of the DCM (Part I) 16
Variable Phase Shift Timing
Start new phase shift
operation. Shift by
one phase increment.
The timing to complete a phase
shift operation varies. PSDONE
indicates operation is complete.
PSCLK
PSEN
PSINCDEC
PSDONE
0 = Decrement phase shift
1 = Increment phase shift
Operation complete.
Okay to start new
operation.
STATUS[0]
(Variable Phase
Shift Overflow)
LOCKED remains asserted during
a variable phase shift operation
Secrets of the DCM (Part I) 17
If phase shift incremented or
decremented to limit value,
STATUS[0] stays High until new
operation shifts away from limit.
Phase Shift Mathematics
Convert Negative Phase Shift to Positive Phase Shift



 PS  360  (PS )
Alternate Phase Shift Solutions



120  CLK0  120  CLK180  60
Convert Phase Shift in Degrees to Phase Shift in Nanoseconds
PS  1000
PS(ns) 

~ 30 to 60ps

360 FCLKIN
Secrets of the DCM (Part I) 18
Lesson Five
Clock Synthesis
Frequency Synthesis
F
F
FPGA
DCM
DCM
F
n
F
F
Fm
Clock Multiplication
Clock Division
High-speed serial data
down-converted to
slower parallel data
n-bits
wide
m-bits
wide
Slower parallel data
up-converted to highspeed serial data
Overclocked,
time-shared logic
DCM
F
Secrets of the DCM (Part I) 20
Low cost design
technique: Utilize full
Clock Synthesis performance of the FPGA
Fx
F
Frequency Synthesis
Output clocks are phase aligned
when using clock feedback via
the CLKFB input.
De-skewed Clock
CLKIN
CLK0
DCM
CLKFB
CLK2X
CLK2X180
CLKDV
F=FCLKIN
50% duty cycle when
DUTY_CYCLE_CORRECTION=TRUE
Clock Doubler
F=2FCLKIN
50% duty cycle
Output available only when
DLL_FREQUENCY_MODE=LOW
Clock Divider
FCLKIN
F=CLKDV_DIVIDE
Usually 50% duty cycle,
depending on conditions
CLKFX
CLKFX180
Secrets of the DCM (Part I) 21
Frequency Synthesizer
CLKFX_MULTIPLY
F=FCLKIN
CLKFX_DIVIDE
50% duty cycle
Does not require CLKFB input
Clock Synthesis Options
DCM
Functional Feedback
Function Output(s) Frequency
Unit
Required?
Clock
CLK2X
DLL
Yes
Doubler
CLK2X180 2*FCLKIN
Clock
Divider
FCLKIN/DIV
DLL
Yes
Frequency CLKFX
Synthesizer CLKFX180 FCLKIN *M/D
DFS
Optional
Secrets of the DCM (Part I) 22
CLKDV
Clock Divider
• CLKDV output requires the DLL and consequently the
CLKFB feedback
• For Spartan-3, the CLKDV_DIVIDE attribute can be …
– 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11,
12, 13, 14, 15, 16
• Lower output jitter when CLKDV_DIVIDE is an integer
• 50% duty-cycle output usually
– Except when operating in High Frequency mode and
CLKDV_DIVIDE is a non-integer (i.e., 1.5)
Secrets of the DCM (Part I) 23
Digital Frequency Synthesizer
(DFS)
• CLKFX/180 output frequency controlled by fraction of two
attributes
– CLKFX_MULTIPLY = {2,3,4• • •32}
– CLKFX_DIVIDE = {1,2,3,4• • •32}
– Reduce to least common multiple
• CLKIN and CLKFX/180 outputs are more limited when also using
the DLL
If only using the CLKFX or CLKFX180
– Using the DLL with the DFS
limits the frequency range
• When used, DDL and DFS are
phase aligned every
– CLKFX_DIVIDE cycles of CLKIN
– CLKFX_MULTIPLY cycles of CLKFX
Secrets of the DCM (Part I) 24
clock ouputs, optionally click None to
extend the DCM frequency limits.
Feedback
Source:
Value:
Internal
1X
External
2X
None
(from General Setup window)
Period Jitter on CLKFX
• Maximum period jitter for CLKFX output is characterized
–
–
–
–
–
Depends on multiply and divide values
Depends on input and output frequencies
Room temperature (25°C)
Nominal voltages
50% CLBs and 40 simultaneous outputs switching at 100 MHz
• Jitter reported by Clock Wizard
• Spartan-3 jitter is effectively same as Virtex-II Pro
http://www.xilinx.com/applications/web_ds_v2/jitter_calc.htm
Secrets of the DCM (Part I) 25
Spartan-3 CLKFX Jitter
Equations
CLKFX/CLKFX180 Output Frequency
 CLKFX_MULT IPLY
FCLKFX  FCLKIN  
 CLKFX_DIVI DE



Peak-to-peak Period Jitter (Unit Interval)
K

Jitter(UI)  0.0006  FCLKFX(MHz)    B  
32 

B = 0.05 when FCLKIN > 8 MHz, else = 0.04
K =CLKFX_MULTIPLY when CLKFX_MULTIPLY > CLKFX_DIVIDE,
else = CLKFX_DIVIDE
Peak-to-peak Period Jitter (ns)
 1000
Jitter(ns)  Jitter(UI)  
F
 CLKFX(MHz)
Secrets of the DCM (Part I) 26




Jitter on CLKFX
Xilinx Clocking Wizard - Clock Frequency Synthesizer
DFS_FREQUENCY_MODE
Valid Ranges for Speed Grade -4
CLK0
CLKFX
CLKFX180
If using only the
CLKFX or CLKFX180
clock outputs, uncheck
CLK0 to extend the
DCM frequency limits
Check CLKFX or
CLKFX180 to enable
the Frequency
Synthesizer options
Displays the incoming clock
frequency, specified earlier
DFS
Fin (MHz)
Fout (MHz)
Low
24.000 - 165.000
24.000 - 210.000
High
48.000 - 280.000
210.000 - 280.000
Inputs for Jitter Calculations
Input Clock Frequency: 33.000 MHz
Enter the desired output
frequency, in MHz or ns,
then click Calculate. DCM
Wizard calculates the best
multiply (M) and divide (D)
values possible.
Use output frequency
MHz
87
Feedback
Source:
Value:
Internal
1X
External
2X
Optionally, enter the specific
values for the multiply (M)
and divide (D) values, then
click Calculate
4
CLKFX_MULTIPLY
CLKFX_DIVIDE
Generated Output
CLKFX_MULTIPLY
M
D
Output
Frequency
(MHz)
Period Jitter
(pk-to-pk ns)
Period Jitter
(unit interval)
29
11
87
1.12
0.10
CLKFX_DIVIDE
Click here for help on
this screen
< Back
DCM attribute name
Secrets of the DCM (Part I) 27
After entering the desired
output frequency or multiply
and divide values, click
Calculate to compute the
resulting jitter for the
Frequency Synthesizer output
1
D
Calculate
None
(from General Setup window)
ns
Use Multiply (M) and Divide (D) values:
M
If only using the CLKFX or CLKFX180
clock ouputs, optionally click None to
extend the DCM frequency limits.
Displays the frequency limits
for the Frequency Synthesizer
in both low- and highfrequency mode
Finish
Displays the calculated output
jitter values based on the
settings
More Info
Cancel
Click Finish
when finished
Cascading DCMs
• DCMs can be cascaded, but there is no dedicated
routing available for this
– The specified output jitter from the first DCM must not exceed
the specified input jitter of the second DCM
– CLKFX output practically eliminated for the first DCM stage
due to jitter
• Keep second DCM reset until first DCM locks
– WARNING: CLKDV does not toggle until LOCKED1
– Requires three flip-flops to synchronize reset
http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=19005
• Function also available in the DCM Wizard
Secrets of the DCM (Part I) 28
Clock Wizard Cascade DCMs
Secrets of the DCM (Part I) 29
Lesson Six
System vs. Source
Synchronous Design
System Synchronous
DATA_OUT
DATA_IN
Clock
Source
• Assumes a single, system-wide clock
• DLL path includes delay to compensate for clock path
– Ensures no hold time requirement at the receiver
• System synchronous is the default assumption
Secrets of the DCM (Part I) 31
Source Synchronous
DATA_OUT
Clock
Source
•
•
•
•
DATA_IN
DATA_CLK
Clock generated by same source as data
Typically, clock and data have same phase
No compensation for clock path delay
Receiver hold time is not an issue
– Clock MUST be phase shifted in the receiver
Secrets of the DCM (Part I) 32
System vs. Source
Synchronous Timing
Data capture window
or data “eye”
DATA_IN
SYSTEM_SYNCHRONOUS
SOURCE_SYNCHRONOUS
SOURCE_SYNCHRONOUS
+ Fixed or Dynamic Phase Shift
Application phase shifts
clock to middle of data eye
Secrets of the DCM (Part I) 33
A little extra delay guarantees no
hold time requirement
Deskew Adjustment in
Clock Wizard
Controls how much skew is
purposely added to the DCM
clock path
Xilinx Clocking Wizard Advanced
Click for Advanced
options
Feedback Value
1X
< Back
2X
Advanced ...
More Info
Next >
Cancel
DCM Deskew Adjust:
SOURCE_SYNCHRONOUS
DESKEW_ADJUST
Wait for DCM lock before DONE signal goes High
Divide Input Clock by 2
Insert reset logic for external feedback
More Info
(from General Setup window)
OK
DCM attribute name
Secrets of the DCM (Part I) 34
Cancel
Lesson Seven
Optional Divide by 2
Dividing Input Clock by 2
• Optional divide-by-2 function on CLKIN input
– Dedicated high-speed toggle flip-flop inside the DCM
• Divide down a high-frequency clock to the range
acceptable to the DCM
• Clean up a non-50% duty-cycle input to
guarantee a clean 50% clock input
– 50% to 60% duty-cycle improves DLL performance
– Low/high duty cycles will stop the DCM working
• See data sheet for specs
Secrets of the DCM (Part I) 36
Divide-by-2 in
Clock Wizard
Xilinx Clocking Wizard Advanced
Click for Advanced
options
Feedback Value
1X
2X
Optionally divides CLKIN
DCM Deskew Adjust:
frequency by 2
SYSTEM_SYNCHRONOUS
Wait for DCM lock before DONE signal goes High
Advanced ...
More Info
Next >
Cancel
Divide Input Clock by 2
CLKIN_DIVIDE_BY_2
Insert reset logic for external feedback
< Back
More Info
(from General Setup window)
OK
DCM attribute name
Secrets of the DCM (Part I) 37
Cancel
Lesson Eight
622 Mbps Interface: Pulling
it all together
Spartan-3 DCM Errata
• CLK2X feedback
– Fixed on XC3S50 and XC3S1000
– Coming on remainder of Spartan-3 family in 2005
• Negative phase shift (No longer an issue)
• Maximum DLL frequency in High Frequency
mode
Secrets of the DCM (Part I) 39
Problem Statement
• We want to build a LVDS transmitter operating at
622 Mbps with a 311 MHz input clock
• Issues:
– Probably NONE
• DCM not required as long as the input clock has roughly
50% duty cycle
• Transmitter macros with embedded FIFO are available for
the Spartan-3 in 4:1, 6:1, 7:1 and 8:1 SERDES factors
• Transmitter macros are also available without the FIFO for
designs that use the DCM
Secrets of the DCM (Part I) 40
622Mbit/second DDR
Transmitter Example
FPGA
FDDRCPE
D0
100W
IBUFGDS_DIFF_OUT
BUFG
311 MHz
D1
CE
C0
C1
BUFG
OBUFDS
311 MHz
Q
No resistors
required for
differential
transmitters.
Clock output shown – data outputs are similar
Secrets of the DCM (Part I) 41
Problem Statement
• We want to build a LVDS receiver operating at
622 Mbps with a 311 MHz input clock
• Issues:
– We have and need a 311 MHz clock
– We need phase shifting, which requires the DLL
– It is a DDR application
• Worry about jitter and duty-cycle distortion
Secrets of the DCM (Part I) 42
Typical 622 Mbps DDR
DCM Configuration
DDR interface uses
half-rate clock
311 MHz
311 MHz
CLKFB
CLK0
CLKIN
CLK180
Phase shift control
Exceeds DLL
maximum phase shift
frequency of 165 MHz
Secrets of the DCM (Part I) 43
Exceeds DLL
maximum
frequency
Fundamental Problem
• 311 MHz forwarded clock coming right at us!
• Spartan-3 DCM supports shifting if CLKIN ≤ 165 MHz
• What to do?
– Use the dedicated divide by 2 option at the input of the
DCM
• Clock applied to the DLL in the DCM will be 155.5 MHz
• Guarantees 50% duty-cycle  DCM Friendly!
– Phase shifting is performed with DCM in low-frequency
mode
– Use the 2X and 2X180 DCM outputs to reproduce to the
required 311 MHz once phase shift has been applied
Secrets of the DCM (Part I) 44
Example 622 Mbps DDR
DCM Configuration
DDR interface uses
half-rate clock
311 MHz
311 MHz
CLKFB
CLK2X
CLKIN
CLK2X180
Phase shift control
Because input clock is 311
MHz and further reduced
with optional divide-by-2,
DCM support phase
shifting
Clock double
reproduces original
input frequency
CLKIN_DIVIDE_BY_2=TRUE
Reduces 311 MHz
incoming clock to <165
MHz, placing DCM in
low-frequency mode
CLK2X output supports up
to 330 MHz!
NOTE: Double jitter as well
• Some devices require additional BUFG due to CLK2X feedback errata
Secrets of the DCM (Part I) 45
CLK0 feedback required for specific
part numbers. Optionally, use
general-purpose interconnect but
phase alignment not guaranteed.
Phase shifter operates
at up to 165 MHz.
155.5 MHz
100W
DCM
IBUFGDS
311 MHz
BUFG
CLKIN
CLKFB
CLK0
BUFG
The CLKIN_DIVIDE_BY_2
option reduces the effective
DCM frequency to 155.5 MHz,
which is within the DCM’s
frequency limits.
100W
IBUFDS
622 Mbps
LVDS/RSDS
receiver
termination
resistor.
CLK2X
CLK2X180 311 MHz
BUFG
CLKIN_DIVIDE_BY_2= TRUE
DLL_FREQUENCY_MODE= LOW
CLK_FEEDBACK= 1X
CLK2X, CLK2X180 outputs
limited to 330 MHz, maximum.
FDCPE
D
CE
C
Q
DETAILED VIEW
FDCPE_1
D
CE
C
Q
FPGA
Secrets of the DCM (Part I) 46
Problem Re-Statement
• We want to build a LVDS receiver operating at
622 Mbps with a 311 MHz input clock
• Issues solved :
– Phase shifting is indirectly available at 311 MHz
– Receiver macros are available for Spartan-3 at 1:4,
1:6, 1:7 and 1:8 SERDES factors
– Setup and hold ‘eye’ parameters do still require
characterization
Secrets of the DCM (Part I) 47
XAPP462: The DCM Reference
• A comprehensive 68page “tree killer”
• Updated for ISE 6.3i and
latest Spartan-3 DCM
knowledge
www.xilinx.com/bvdocs/appnotes/xapp462.pdf
Secrets of the DCM (Part I) 48
Questions?
[email protected]
Secrets of the DCM (Part I) 49
Please Fill Out and Return the
Feedback Forms!
• Forms are in the back of your FAE conference book
• Please return at back of the room
Secrets of the DCM: Part 2
Steve Knapp



Secrets of the DCM (Part I) 50
Jump Point
• Lesson 4: Phase Shifting
• Lesson 5: Frequency Synthesis
• Lesson 6: System vs. Source Synchronous
• Lesson 7: Optional CLKIN divide-by-2
• Lesson 8: Spartan-3 622Mbps Design Example
• Session Evaluation Forms
Return to last slide viewed
Secrets of the DCM (Part I) 51