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TFT(Thin Film Transistor) LCD II Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 Contents • TFT-LCD Overview – Structure of TFT-LCD Panel (Back Light System, Polarizer, Color Filter) – Pixel Structure – TFT Fabrication – TFT-LCD Driver (Data & Gate Driver) and Interface System Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 • Issues and Technologies of TFT-LCD – – – – – High Gray Scale Low Power Consumption High Aperture Ratio Wide Viewing Angle Large Size Display Gray Scale Generation • Various gray scale generation Methods – Decoder-Based DAC – Resistor-String DAC – Capacitor DAC Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 • Weighted Capacitance Type DAC • Split Weighted Capacitance Type DAC • C-2C Type DAC – Ramp Method – Dithering Method – FRC(Frame Rate Control) – Shindou Method Digital Data Driver _Decoder Based DAC • DAC Using Decoder • Pros 3bit data V0 V2 V4 V6 – Clear and fast operation – Relatively simple circuit • Cons Hanyang University V1 V3 V5 V7 Integrated Electronics Laboratory O. K. Kwon Nov. 2000 – As many external voltage sources and analog switches Pass Decoder gate as gray scales array – Many voltage source : High system costs – Many analog switches : Large area 3-to-8 decoder based DAC – Impractical for high gray scale Digital Data Driver_Resistor String DAC • 8 bit Resistor String DAC VREF1 VREF2 – External voltage sources – 8-resistor string between neighboring voltage sources • 256 analog voltage levels D0 D1 D2 D3 D4 D5 D6 D7 VREF(N-1) VREF(N) Hanyang University OUT Integrated Electronics Laboratory O. K. Kwon Nov. 2000 • Pros – Less voltage sources than decoder-only type – More accurate than capacitor DAC • Cons – Static currents – Difficult to implement accurate resistance – Area increase with gray scale Reference Generator ROM Type Decoder 8-bit resistor string DAC Digital Data Driver_Capacitor DAC - 16/15C + C Reset C 2C 4C C 8C 2C 4C Vout 8C VREF1 Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 VREF2 • Capacitor DAC – Analog voltage generation controlling charge sharing between capacitors – Binary weighted capacitor • Pros • Cons – No static current – Less external voltages (1 or 2) – Easier to control thermal oxide thickness Uniform capacitors – Large area : DAC unit at every line – Variable data line capacitance • When OP-AMP not used – Less accurate than R-DAC Digital Data Driver_C-2C DAC Reference voltages 2C 2C — D7 — D6 — D5 C Hanyang University C C C D0 D1 D2 D3 D4 VO C Integrated Electronics Laboratory Vr- Reference voltage selector (upper 3-bit decoder) • • C O. K. Kwon Nov. 2000 Vr+ • 2C 2C VrVr+ 5-bit C-2C DAC 8-bit D/A Converter with -correction – Reference voltages can be adjusted to the LCD’s non-linear V-T characteristics Small area of DAC compared with weighted capacitor type Power consumption is reduced Digital Data Driver_Ramp method • • • DAC Using Ramp Signal : 6Bit Structure – Shift register, Input register, Storage register, Counter, Analog switch – Externally supplied ramp signal Operation – When a counter counts up to 111111, it turns-off the analog switch. – If an input data is 111111, the analog switch is turned-off as soon as the data is loaded – If an input data is 000000, the analog switch keeps being turned-on until the counter counts from 000000 to 111111. – The counter determines when to turnoff the switch Hanyang University Integrated Electronics Laboratory Data Input register Load Clock 5-bit counter External ramp O. K. Kwon Nov. 2000 External ramp Counter Output DAC Output Data= 000010 Data= 111101 Digital Data Driver_Ramp method • Cons • Pros – -correction by control of voltage step V1, V2 , V3 (See below) – No resistor, capacitor or amplifier Better uniformity T(%) – Complex circuitry ( 6bit counter at every data line ) – Ramp signal distortion due to RC delay and noise Counter Output 000 V7 Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 100 001 010 011 100 101 110 Time V6 V1 80 V5 V2 V4 60 V3 V3 V3 V3 40 V2 V2 20 External Ramp V1 V1 V0 0 1 2 3 4 V-T characteristics of LC V(volt) 5 V-T nonlinearity compensation using ramp signal 111 Digital Data Driver_Dither method Brightness(gray scale) Driving Voltage and Gray Scale by 8-voltage levels by Dither-method Gray Scale Interpolation using Dither-Method 12 12 16 12 16 12 16 16 16 16 12 12 12 12 12 16 12 16 16 16 16th 12th 12th • V1 V2 V3 V4 V5 V6 V7 V8 Driving voltage • Cons – Reduced resolution Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 13th 14th 15th 16th Principles – V4 represents 12th gray, V5 represents 16th gray – Group 4 pixels as a unit – 4 pixels select 12th gray, 12th gray on average – 3 pixels select 12th gray, 13th gray on average – 2 pixels select 12th gray, 14th gray on average – 1 pixel select 12th gray, 15th gray on average – All pixels select 16th gray, 16th gray on average Digital Data Driver_Frame Rate Control Gray Scale Using FRC High-Level Gray-scale 1 2 3 4 V0 V0 V0 V0 V1 V0 V1 V0 Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 Low-Level Gray-scale V0 V2 V0 V2 Transmittance(arb.unit) Frame Gray-Scale White 4-level V-T characteristics 10 a b 1 2 2 2 V0 + V1 c 1 2 2 2 V0 + V2 1 d 2 2 2 V1 + V2 1 Black V1 V2 V1 V2 V0 V1 V2 Voltage(rms) • • Frame Rate Control - Temporal average Cons • Principle 1 rms V 02 + V 12 – Should increase to prevent flicker – V0, V1 alternation : 2 1 – High speed addressing required – V0, V2 alternation : rms V 02 + V 22 2 unsuitable for high gray scale Digital Data Driver_Shindou method[1/2] • Principle – Alternation of Vi, Vj of which duty ratio is m:n m Vi + nVj V – Average voltage transferred to pixel average m+n – Controlling m and n : interpolation between Vi and Vj m n Vi Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 Vj • Theoretical Background – An periodic function f(x) can be expressed in Fourier series a0 f (x) + (an cos nx + bn sin nx ) 2 n 1 1 1 an f ( x ) cos nxdx, (n 1,2,3, . . . .) bn f ( x ) sin nxdx, (n 1,2,3, . . . .) - - – Data line and pixel act as a low pass filter – Harmonics are suppressed and DC (average value) component are transferred to pixel TM4 TM3 TM2 TM1 TN0 V0 V32 V64 V128 V96 V160 V192 V224 V256 TM4 TM3 TM2 TM1 TN0 Digital Data Driver_Shindou method[2/2] D0 S0 ASW0 D0 D0 D1 S32 ASW32 D1 D1 D2 S64 ASW64 D2 D2 D3 S96 ASW96 D3 D3 D4 S128 ASW128 D5 S160 ASW160 D6 S192 ASW192 D7 S224 ASW224 D8 S256 ASW256 SCC Output Stage Using Shindou Method OUT D4 D4 16T TM4 T IS ISG D5 D5 Hanyang University S0 S0 S32 S32 TM3 S64 S64 S96 S96 TM2 S128 S128 S160 S160 S192 S192 S224 S224 S256 S256 Integrated Electronics Laboratory O. K. Kwon Nov. 2000 D6 D6 D7 D7 8T 4T 2T TM1 T TM0 SC Structure of SCC Waveforms of TMs • Operation – SC selects neighboring two voltage sources according to higher 3bits D5, D6, D7. – ISG generates 32 kinds of pulse T whose duty ratios are 31:1~0:32 using TMs according to lower 5bits D0, D1, D2, D3, D4, D5. – The selected two voltage levels are interpolated by the generated pulse T Issues and Technologies for High Gray Scale • Issues – Vp compensation • Capacitor coupling structure • Vp compensation structure – Random offset of the output buffer Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 • Offset compensation structure – Area Increases of the DAC • Compact DAC data driver (SID ’00) • New Driving Method for 8bit gray scale is needed Vp problems • Vp problem(Gate Voltage Feedthrough) VD VGn VGn-1 Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 CS VD CLC VP VP VP VP CGD VGn VP VG CGP CGP + CS + CLC Vp problems • What troubles in Vp ? CGS 1 VG V P Uneven parasitic capacitance in all pixels CLC + CSTG + CGS 1 Asymmetric charging characteristic Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 Uneven Vp in all pixels Degradation of gray scale • To reduce Vp – Pixel design optimization – Vp compensation circuit too complex – Novel methods are needed. Vp Compensation Driving • LC voltage at the end of selection VLC Vcol - Vg CGS CGS CST C + Vcomp Vcomp Vg GS for compensation + CLC + CS CGS + CLC + CST CST Vg,n Column Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 Row n Vg,n CGS t Vg,n-1 Tr CLC Row n-1 Vcomp t Vg,n-1 CST Random offset of the output buffer • Random Offset Process variations between channel-to-channel, chip-to-chip, wafer-to-wafer Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 Without Offset Cancellation Technique Decrease of Yield Difficult With Offset Cancellation Technique Random offset of the output buffer • Why Difficult ? – Different loads of OP-AMP • Calibration mode < 1pF • Driving mode > 100pF Driver Vin – Difficult to design OP-AMP Vos Integrated Electronics Laboratory O. K. Kwon Nov. 2000 • Solutions – OP-AMP with internal offset calibration OP-AMP SW2 Hanyang University TFT-LCD Panel Loads C SW1 SW3 loads < 1pF loads > 100pF – External offset calibration technique – Driving methods insensitive to offset voltage Common Offset Cancellation Circuit Area Increases of the DAC • DAC – Resistor String DAC – Capacitor DAC etc. Resistor String V8 R255 Rom Type Decoder doubled DAC area (in resistor 1-bit increase string DAC) V255 Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 V254 R254 V253 8-bit DAC Area R253 V252 R252 10-bit DAC Area V251 4 times larger R04 V04 R03 V03 • Solutions - New DAC schemes R02 V02 R01 V01 R00 V0 V00 D0 D1 D2 D3 D4 D5 D6 D7 8-bit DAC Vout Digital Data Driver_Area-efficient driver [1/2] Control Logic 36 Data Vgamma 8 6-Bit DAC (6 Stage) Analog Sample Circuit Analog Hold Circuit Buffer Analog Sample Circuit Analog Sample Circuit Analog Sample Circuit Analog Sample Circuit Analog Sample Circuit Analog Sample Circuit Analog Hold Circuit Analog Hold Circuit Analog Hold Circuit Analog Hold Circuit Analog Hold Circuit Analog Hold Circuit Buffer Buffer Buffer Buffer Buffer Buffer DRV OUT<1> DRV OUT<2> DRV OUT<3> DRV OUT<4> Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 DRV DRV OUT<383> OUT<384> Compact(Area Efficient) LCD Driver • Operation – Once the data are converted to parallel, they are fed into six DACs – The result is six analog voltages, which are multiplexed onto sample and hold cells, one for each output Digital Data Driver_Area efficient driver [2/2] • Pros – Area-efficient • 6bit * 384 DACs are needed for conventional data driver • 6bit * 6 DACs + 384 sample and hold circuits for compact driver – Low power consumption because of the reduced static currents of DACs Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 • Cons – Sample and hold circuits errors are included (inapplicable to high gray scale) Low Power Consumption • Overview Reduction of panel load driving power Improvement of transmission rate of panel • Improvement of panel aperture ratio • High transmission rate color filters, polarizers Backlight Unit 60% Improvement of light utilization rate • Efficiency improvement of light guides • Improvement of light emission efficiency of CCFT • Panel load capacity reduction • Energy recovery driving • Reduced frame rate Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 Circuit Unit 40% Low voltage drive circuits • 5V 3.3V Excellent-efficiency power supply circuit • Efficiency improvement of DC/DC converter Power Breakdown of Data Driver Black and White Vertical Stripe Black Polarity Inversion Analog DC Power (VDDa=10V) Digital Power Line/Dot Column Line/Dot Column 145mW 145mW 145mW 145mW Hanyang University Power Consumption Panel AC Power Integrated Electronics Laboratory O. K. Kwon Nov. 2000 5mW 5mW 15mW 15mW 14mW 14mW 21mW 21mW 275mW 0.52mW 139mW 0.34mW 439mW 164mW 320mW 181mW Analog DC Power (VDDd=2.5V) Interface Bus Power Panel AC Power Total (12.1 inch SVGA ,SID ’97) Interface Bus Power Digital Power Low Power Driving(AC Power Reduction) • Equation of the Panel AC Power Consumption PAC VDD I AVE F VDD NS CL VSWING ROW 2 Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 • Two approaches to reduce AC power Reduce FROW •MFD(Multi-Field Driving) Reduce VSWING •Charge Sharing •Triple Charge Sharing •Stepwise Source Driving •RLC Resonant Method Low Power Driving - Multi-Field Driving [1/3] • Background – Total power consumption (TPC) = Static power consumption (SPC)+Dynamic Power Consumption (DPC) – DPC is 70% of TPC, so refresh rate must be slow down for TPC reduction, because DPC is directly proportional to refresh rate Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 – Slower refresh rate causes more visible flicker! Multi-Field Driving Field 7 6 3 2 1 1 2 3 4 5 • Multi-Field Driving Method – Divide 1 frame into 3 sub-field – The polarity of adjacent field is opposite – In spite of reduced refresh rate, Flicker frequency remains at the same level due to averaging effect Low Power Driving - Multi-Field Driving [2/3] i(t) i(t) VN VP ia(t) Ts VS 2 3 Ts VS VS 2nTs (2n+1)Ts (2n+2)Ts t t (b) (a) (a) Flicker for one line Hanyang University O. K. Kwon Nov. 2000 (b) Flicker for adjacent three lines • Flicker Compensation – – – – Integrated Electronics Laboratory t (c) (C) Average flicker for adjacent three lines In the case that refresh rate is reduced from 60Hz to 20Hz Flicker frequency for each line : 2TS (three times longer than original one) Flickers for adjacent three lines occur at different phase Average flicker frequency for three serial lines : 2/3 TS In spite of reducing refresh rate into 1/3 of original one, flicker frequency remains at the same level Low Power Driving - Multi-Field Driving [3/3] • Power Consumption Reduction • Pros. 100 Dynamic Power Consumption - power saving efficiency > 50% Static Power Consumption 45 Hanyang University Integrated Electronics Laboratory Power(%) O. K. Kwon Nov. 2000 50 15 • Cons. 55 7 5 5 - Inapplicable to moving image 19 18 16 - extra frame memory 13 - complex 34 1 3 5 11 Interlaced Subfield Images Low Power Driving - Charge Sharing [1/2] Waveform and timing diagram Architecture #M row line time Charge Sharing time Conventional Data Driver #M+1 row line time Charge Sharing Gray Scale time Decision time Charge Gray Scale Sharing Decision time time VDD AMP CR Positive Video Signals Hanyang University VH 1 V 2 swing Integrated Electronics Laboratory O. K. Kwon Nov. 2000 Panel RL CL 1 RL RL CL 2 CL 3 • Operation RL CL 4 RL CL N-1 RL CL N Vcom Negative Video Signals VL GND CR – Now Mth row was driven and (M+1)th row is about to be driven – Neighboring data lines store video signals of opposite polarities – Shortly before driving Mth row, every switch is disconnected from output buffer and connected to CL – Every data line has medium voltage level due to charge sharing – Signal CR controls the switches Low Power Driving - Charge Sharing [2/2] • Power Consumption Analysis Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 Power Saving Efficiency [%] – Vpos voltage level of video signal of positive polarity – Vneg voltage level of video signal of negative polarity 50 – Half of Vswing is supplied by charge sharing and only the other half comes from the external source PCh arg e -Sharing 40 30 0.1s 0.2s 0.3s 0.4s 0.5s 20 10 0 0.4 • Pros. 0.6 0.8 1.0 charge time [ s] - applicable to moving image - no degradation of image quality FROW 1 VDD [ N CL Vswing ] - very simple 2 2 - power saving efficiency < 50% 1 •Cons. PAC 2 - power saving efficiency < 50% Low Power Driving - Triple Charge Sharing [1/3] Waveform and Timing Diagram SEL1 AMP SEL2 SEL3 Architecture #M row line time Triple charge sharing CEXT Conventional Data Driver Gray Scale Decision time VDD Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 Positive Video Signals VH Vcom Negative Video Signals VL New Driver GND RL RL RL RL RL CL 1 CL 2 CL 3 CL N-1 CL N Panel SEL1 SEL2 SEL3 1 V 3 swing Vswing #M+1 row line time Triple charge sharing Gray Scale Decision time Triple charge sharing Low Power Driving - Triple Charge Sharing [2/3] • Convergence of the voltage of CEXT V DD VH Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 V SWING after thousands of row line time V EXT V SWING 3 VL GND 500 If CEXT N CL 1000 1500 2000 time [ X row line time ] VEXT 1 VL + VSWING 3 SEL1 AMP SEL2 SEL3 Low Power Driving - Triple Charge Sharing [3/3] #M row line time Triple charge sharing CEXT Gray Scale Decision time Triple charge sharing VDD Conventional Data Driver Positive Video Signals VH Vcom Negative Video Signals New Driver Gray Scale Decision time #M+1 row line time Triple charge sharing Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 1 3Vswing Vswing VL GND SEL1 RL RL RL RL RL CL 1 CL 2 CL 3 CL N-1 CL N Panel SEL2 SEL3 AMP 1 P PAC Power consumed in Gray Scale Decision Time : TRIPLE _ CHARGE _ SHARING 3 • Pros. - applicable to moving image - no degradation of image quality - simple - power saving efficiency < 66.6% • Cons. - row line time extension method is needed Low Power Driving - Stepwise Source Driving [1/3] 1H 2H 1H 3H 2H 3H VDD (10V) VDD (10V) C VH positive video B VCOM (5V) negative video positive video VCOM (5V) 5.5V Hanyang University D Integrated Electronics Laboratory O. K. Kwon Nov. 2000 VL negative video A GND GND fully supplied by amplifier (VDD) Conventional Source Driving Power supply amplifier Stepwise Source Driving Voltage A B C D swing Power Polarity Polarity amplifier amplifier supply modulator VL modulator VH Low Power Driving - Stepwise Source Driving [2/3] • Schematic Diagram SW5 7.75V VH SW4 AMP_H AMP_L AMP_H AMP_L AMP_H AMP_H AMP_L AMP_L 6.65V CT4 SW3 Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 MUX_A 5.55V CT3 MUX_A MUX_A MUX_A MUX_A MUX_A MUX_A EO SW2 4.45V CT2 CLOAD PM Odd PM Even MUX_B SW1 MUX_B MUX_B MUX_B MUX_B MUX_B MUX_B CON 3.35V CT1 SW0 PIXEL Polarity Modulator Architecture of Driver 2.25V VL Low Power Driving - Stepwise Source Driving [3/3] • Pros. Waveform in All-Black image 1H 2H VDD black VH VL black black Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 polaity modulation polaity modulation gray scale decision Waveform in All-White image 1H white gray scale decision • Cons. 2H VH white VL polaity modulation gray scale decision polaity modulation - applicable to moving image - no degradation of image quality - power saving efficiency < 84.5% white gray scale decision - row line time extension method is needed - voltage overcharging Low Power Gate Driving_RLC Resonant Method [1/2] • Operation Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 + - – RLC resonant operation whose oscillation is interrupted after half oscillation – Oscillation sensing circuitry sense the ON-resistance of the switch L VS/2 CL Simplified Structure Schematic View of Driving Circuitry Low Power Gate Driving_RLC Resonant Method [2/2] • Operation time range – Charging (discharging) time is divided into two oscillation time and two charge sharing time Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 • Power dissipation VLOST 4 VS C pix NL tSWING C pix LN PrlcR VSVLOST C pix fN • Applicable to gate and data driver of LCD Timing diagram Low Analog DC Power_Class-B Buffer • Operation – Nonlinear circuits are included (inverter and comparator) – Output NMOS and PMOS are turned on by series-shunt feedback of input/output voltage VDD Vos1 Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 Cmp1 Vout Vin • Pros – Low static current Vos2 Cmp2 • Cons – Sensitive to the offset voltage of comparators VSS Block diagram of class-B output buffer High Aperture Ratio TFT • Aperture ratio decreases as pixel pitch shrinks • Use of Black matrix – Prevent light transmittance through a pixel surrounding area Gate Line Black matrix Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 • High aperture ratio structure Data Line Storage Capacitance – Shield CS(storage capacitor) structure Aperture Area – ITO Shield Plane structure Aperture of a Single Pixel High Aperture Ratio • Shield-CS structure – Shield-CS pattern(electro-static layer) functions as a common electrode of a storage capacitance – Coupling capacitance between the signal line and the pixel electrode can be reduced – This permits close layout between signal electrode and the pixel electrode Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 • ITO-shield plane structure – Transparent electrode is placed between the signal line and the pixel electrode – This electrode works as a ground plane and shields capacitive coupling – Transverse electric field is reduced due to the same reason as the shield CS High Aperture Ratio Aperture Area Conventional Structure Alginment margin Signal Line Black Matrix Aperture Area Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 Shield -CS Signal Line Alginment margin Shield Cs ITO Shield Plane Liquid Crystal Signal Line No Black Matrix Pixel Electrode Shield and storage capacitance electrode Insulator High Aperture Ratio Black matrix CS Conventional Structure 50 ~ 70% Aperture area Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 Shield -CS 70 ~ 80% ITO Shield Plane 80 ~ 90% Wide Viewing Angle • Conventional TN Structure – Anisotropic Structure of LC molcule – Imperfect light control (Use of Polarizer) – Viewing angle dependence is intrinsic problem of LCD – Gray scale inversion occurrs Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 Viewing Angle 90°(H), 40°(V) Aperture Ratio 50~70% Wide Viewing Angle • Vertical Alignment Mode • Advantages – Wide viewing angle without gray scale inversion – High contrast ratio(~300:1) – Fast response time(~25ms) Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 • Disadvantages – Material Limitation(LC) – Use of compensation film – Adoption of multi-domain technology – Complicate LC process – Unstable alignment to mechanical shock Viewing Angle 140°(H), 120°(V) Aperture Ratio > 80% Wide Viewing Angle • In-Plane Switchig • Advantages – Wide viewing angle without gray scale inversion – Low flicker level(Unvisible) – Low cost Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 • Disadvantages – Slow response time(>45ms) – Low transmittance(<4%) – Crosstalk – High driving voltage Viewing Angle 160°(H), 160°(V) Aperture Ratio< 40% Large Panel Size and High-Resolution • Issues – Shortage of the Row Line Time • Solutions Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 – Dual Line Scanning – Display Area Division Scanning – LiTEX(Line Time Extension) Row Line Time and Resolution Large-Size High -Resolution Increase of parasitic loads Increase of RC charging time Decrease of row line time Deterioration of Image Quality Row Line Time (sec) 35 XGA SXGA UXGA QXGA 30 25 Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 20 15 10 5 Needs for Increase techniques of row line time 0 50 55 60 65 70 Frame Rate(Hz) 75 80 Effective Mobility and Resolution 2.5 Effective mobility (Cm2/vs) • Effective mobility : minimum mobility necessary to achieve the maximum aperture ratio • Effective mobility is increased as panel size is larger • Effective mobility is increased as the resolution of panel is higher XGA SXGA UXGA QXGA 2.0 Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 1.5 1.0 0.5 0.0 150 200 250 Pixel Pitch (m) 300 Dual Line Scanning Method • Dual Line Scanning Method – Pros. : Doubled Row Line Time – Cons. : Decrease of Vertical Resolution (1/2 of conventional) 1H 1H 1H 1H Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 G1 G2 G3 G4 Driver LSIs • Display-Area division scanning – Pros. : Doubled Row Line Time – Cons. : Cost Increase (Doubled Driver LSIs) TFT-LCD panel Line Time Extension Method • Primitive Scanning Waveforms 1H Conventional Scanning G1 G2 G3 G4 1H Hanyang University 1H Integrated Electronics Laboratory O. K. Kwon Nov. 2000 T1 Extended Line Time LiTEX Scanning G1 G2 G3 G4 T2 Image Differentiation from G1 1H Conclusions • We have surveyed the driving methods and driver circuits. • Reviewed issues and key Technologies – High Gray Scale • New Driving Method for 8bit gray scale Hanyang University Integrated Electronics Laboratory O. K. Kwon Nov. 2000 – Low Power Consumptions • Multi-Field Driving Method • Charge Sharing, Triple Charge Sharing, Stepwise Driving, RLC resonant • Low Analog DC Power : precharging method, Class-B buffer – High Aperture Ratio : Shield-Cs, ITO Shield Plane – Wide Viewing Angle : VA, IPS – High-Resolution : Dual line scanning, LiTEX