Transcript Chapter 5 Sequential Systems

Chapter 5
Sequential Systems
Latches
and Flip-flops
Synchronous Counter
Asynchronous Counter
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Introduction


Up to now everything has been
combinational – the output at any instant of
time depends only on what inputs are at
the time.
Later on of this course: sequential systems
– systems that have memory. Thus, the
output will depend not only on the present
input but also on the past history – what
has happened earlier.
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2
Clock Signals


Two versions of a clock signal are as below.
In the first, the clock signal is 0 half of the
time and 1 half of the time. In the second, it
is 1 for a shorter part of the cycle.
The period of the signal (T on the diagram)
is the length of one cycle. The frequency is
the inverse (1/T).
T
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Conceptual View of
a Sequential System
Clock
q1
x1
...
...
Memory
qm
...
...
xn
z1
Combinational Logic
zk
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Terminology
State: what is stored in memory.
 State table: shows for each input
combination and each state, what the
output is and what the next state is – what
is to be stored in memory after the next
clock.
 State diagram (or state graph): a graphical
representation of the state table.


(Finite) State Machine
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State Table and State Diagram
present
state
q
A
B
C
D
next
state
output
q*
z input
x=0 x=1 x=0 x=1
0
0
A
B
1
0
C
B
0
0
A
D
0
0
C
C
State table
0/0
A
0/0
1/0
B
1/0
0/1
C
0/0
X/0
1/0
1/0
D
State diagram
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


The next state is a function of the
present state and the input.
The output also depends on the present
state (and on the input). It may change
on a clock transition, but it may change
where the input changes, as well.
In state diagram, there must be one
path from each state for each possible
input combination.
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Moore vs. Mealy Models


Moore model circuit (state-based) 
the outputs depend on the present state
of the system but not on the inputs.
Mealy model circuit (input-based) 
the outputs depend on the inputs as
well as the present state of the system.
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

Moore: A system with no input and three
outputs, that represent a number from 0 to 7,
such that the outputs cycle through the
sequence 0 3 2 4 1 5 7 and repeat on
consecutive clock inputs.
Mealy: A system with two inputs,X1 and X2,
and three outputs, Z1, Z2 and Z3, that represent
a number from 0 to 7, such that the output
counts up if X1=0 and down if X1=1 and
recycles if X2=0 and saturates if X2=1. Thus,
the following output sequences might be seen:
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



X1=0 X2=0
X1=0 X2=1
X1=1 X2=0
X1=1 X2=1
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7..
0 1 2 3 4 5 6 7 7 7 7 7 7..
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0..
7 6 5 4 3 2 1 0 0 0 0 0 0..
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Design Process of Sequential
Systems

Table 5.1 Page 338






State table
Timing trace
State table with binary states
Truth table
K-map
equations
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Design Process of Sequential Systems
q
A
State table
q*
z
x=0 x=1 x=0 x=1
0
0
A
B
B
C
B
1
0
C
A
D
0
0
D
C
C
0
0
Timing trace
clk 1
x 0
2
1
3
1
4
0
5
1
6
0
7
1
8
0
9 10 11 12
1 1
q
A
A
B
B
C
D
C
D
C
D
C
z
0
0
0
1
0
0
0
0
0
0
0
0
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Design Process of Sequential Systems
State assignment
q
A
B
C
D
q1 q 2
0 0
0 1
1 0
1 1
State table with binary states
q1
q1*q2*
z
x=0 x=1 x=0 x=1
0
00 00 01 0
0
01 10 01 1
0
0
10 00 11
0
11 10 10 0
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Design Process of Sequential Systems
Truth table for system design
x
z
0
q1q2
x
x’
x
0
q1 q2 q1 * q2 *
0
0 0 0
0
0
1
1
0
1
0
1
0
0
0
0
0
1
1
1
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
1
1
0
0
q1’
q1
1
1
1
q2’
q2
1
q2’
q1*  xq1  xq2
State assignment
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Latches and Flip-flops

A latch is a binary storage device, composed
of two or more gates, with feedback.
The latch can store either
a0
a1
(Q = 0 and P = 1)
(Q = 1 and P = 0)
or
The P output is just labelled Q
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Latches (cont.)
•Edge-triggered
•
rising/leading edge-triggered
•
falling/trailing edge-triggered
•Level-triggered
•
high level-triggered
•
low level-triggered
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Latches (cont.)

Example: a latch constructed with 2 NORs.
S
R
P
Q
The equations for this system:
P  S  Q and Q  R  P
Normal storage stage  both inputs inactive
(S = R = 0).
PQ
and Q  P
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Latches (cont.)
Case 1: If S=1 and R=0
P  (1 Q)  1  0
Q  (0  0)  0  1
S
P
R
Q
Case 2: If S=0 and R=1
Q  (1 P)  1  0
P  (0  0)  0  1
Case 3: Finally, the flip-flop is not operated
with both S and R active (=1).
P  (1 Q)  1  0
Q  (1 P)  1  0
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Latches (cont.)
D flip-flops (Delay flip-flops)
SR flip-flops (Set/Reset flip-flops)
T flip-flops (Toggle flip-flops)
JK flip-flops
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D flip-flops
D q
0 0
0 1
q*
0
0
1
1
1
1
0
1
D q*

0 0
1 1
q*=D
1
0
D
0
1
1
0
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D flip-flops (cont.)
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D flip-flops (cont.)
Two D flip-flops
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D flip-flops (cont.)
With Clear and Preset
PRE C LR D
0
1 X
q
q*
X
1
Static
1
0
X
X
0
Immediate
0
0
X
X
-
Not allowed
1
1
0
0
0
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
Clocked
(as before)
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D flip-flops + Clear and Preset
(cont.)
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SR flip-flops
S
R
q
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
q*
0
1
0
0
1
1
-
S R q*
0 0 q

0 1 0
q*  S  Rq
1 0 1
SR
1 1 S’
q
S
q’
10
q
1
R’
0
00
01
SR
01
R
x
1
x
1
R’
1
00
10
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SR flip-flops (cont.)
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T flip-flops
T
0
0
1
1
q
0
1
0
1
q*
0
1
1
0
T q*

0
1
q*=Tq
q
1
q
0
T
0
1
0
1
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JK flip-flops
J
0
0
0
0
1
1
1
1
K
0
0
1
1
0
0
1
1
q
0
1
0
1
0
1
0
1
q*
0
1
0
0
1
1
1
0
J K q*
0 0 q

0 1 0
1 0 1
1 1 q
JK
J’
q
J
q’
q
1
1
1
K’
1
K’
K
q*  Jq  Kq
10
11
0
00
01
JK
01
11
1
00
10
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JK flip-flops (cont.)
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Analysis of Sequential Systems

Figure 5.21 Page 342







Circuit
Equations
State table
Timing trace
Timing diagram
Equations A*,B*
State diagram
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Flip-flop Design Techniques
x
q1
0
From the truth table, it’s
clear that
0
q2 q1 * q2 *
0
0
0
z
0
0
0
1
1
0
0
0
1
0
0
0
0
0
1
1
1
0
1
1
0
0
0
1
0
1
0
1
0
1
0
q
1
1
0
1
1
0
0
q* Input(s)
0
1
1
1
1
0
1
0
1
1
0
1
1
Main truth table
z=q1q2
We need to create the
appropriate flip-flop design
table to obtain a truth table
for the flip-flop inputs.
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•D flip-flops
•JK flip-flops
•SR flip-flops
•T flip-flops
next
31
Design with D Flip-flop
D q*
0 0
1
1
q
q*
0
D
0
0
1
1
1
0

x q1 q2 D1=q1* D2=q2*
0
0
0 0 0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
1
1
1
0
1
1
1
0
0
0
1
1
0
1
0
1
1
1
0
1
1
1
1
1
1
0
From the main truth table

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Design with D Flip-flop (cont.)
x
q1q2
x
0
1
00
q1q2
00
0
1
1
01
1
01
11
1
11
1
10
1
10
1
D1  xq2  xq1
D2  xq2  xq1
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Implementation using D Flip-flops
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Design with JK Flip-flop
J
0
K q*
0 q
0
1
0
1
0
1
1
1
q

q q* J
K
0
0
0
X
0
1
1
X
1
0
X
1
1
1
X
0
From the main truth table


x q1
0
0
q2 q1 * q2 * J 1
0 0
0
0
K1
X
J2
0
K2
X
0
0
1
1
0
0
X
X
1
0
1
0
0
0
X
1
0
X
0
1
1
1
0
X
1
X
1
1
0
0
0
1
0
X
1
X
1
0
1
0
1
1
X
X
1
1
1
0
1
1
X
0
1
X
1
1
1
1
0
X
0
X
0
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Design with JK Flip-flop (cont.)
x
q1q2
x
0
1
q1q2
0
1
q1q2
00
X
X
00
1
01
X
X
01
00
01
x
11
X
X
11
1
11
10
X
X
10
1
10
J1
x
0
1
q1q2
0
1
1
00
X
X
X
X
01
1
1
X
X
11
1
1
10
X
K1
J2
J1  xq2
;
K1  x
J2  x
;
K2  x  q1
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K2
back
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Design with SR Flip-flop
S R q*
0 0 q
0
1
0
1
0
1
1
-
1

q q* S
R
0
0
0
X
0
1
1
0
1
0
0
1
1
1
X
0
From the main truth table


x q1
0
0
q2 q1* q2* S1 R1
0 0
0
0 X
S2 R2
0 X
0
0
1
1
0
0
X
0
1
0
1
0
0
0
0
1
0
X
0
1
1
1
0
0
1
0
1
1
0
0
0
1
0
X
1
0
1
0
1
0
1
1
0
0
1
1
1
0
1
1
X
0
1
0
1
1
1
1
0
X
0
X
0
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Design with SR Flip-flop (cont.)
x
q1q2
x
0
1
00
x
q1q2
0
1
q1q2
00
X
X
00
x
0
1
q1q2
0
1
00
X
01
1
01
1
01
X
01
11
X
11
1
11
X
11
1
10
X
10
1
10
1
10
X
J1
K1
J2
S1  xq2
;
R1  x
S2  x q2
;
R2  x  q1q2
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1
1
K2
back
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Design with T Flip-flop
T
0
q*
q
1
q
q
q*
0
T
0

0
x
q1
0
0
1
1
1
0
1
1
1
0
From the main truth table

0
q2
0
q1 *
0
q2 *
0
T1
0
T2
0
0
0
1
1
0
0
1
0
1
0
0
0
1
0
0
1
1
1
0
1
1
1
0
0
0
1
0
1
1
0
1
0
1
1
1
1
1
0
1
1
0
1
1
1
1
1
0
0
0
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Design with T Flip-flop (cont.)
x
q1q2
x
0
1
00
q1q2
0
00
01
1
1
1
1
11
10
1
10
T1  xq1  xq1q2
1
01
11
1
1
1
T2  xq2  xq2  xq1q2
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Quick method for JK
Because
q*  Jq  Kq
Notice that when q=0
q*  J 1  K  0  J
 J  q*
And when q=1
q*  J  0  K 1  K
 K  q*
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Quick method for JK (cont.)
state table to maps
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Quick method for JK (cont.)
Conventional
q q* J
0 0 0
K
X
0
1
1
X
1
0
X
1
1
1
X
0

First column
of J1 and K1

Second column
of J1 and K1
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Quick method for JK (cont.)
Computation of J2 and K2 Conventional
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Quick method for JK (cont.)
Computation of J1 and K1 Quick method
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Design of
Synchronous
Counters

Design a decimal or
decade counter using JK
flip-flops:
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, …
D
C
B
A
D* C*
B*
A*
0
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
0
0
1
1
0
1
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
x
x
x
x
… … … … …
…
…
…
1
x
x
x
1
1
1
X
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Design of Synchronous Counters (cont.)
DC
BA
D*
D
X
B
1
C
DC
BA
B
1
X
B
B*
DC
BA
D
X
X
X
B
C
1
C
1
X
1
X
1
C
DC
BA
A
X
D
1
A
D
X
1
B
C
C
1
B
A
X
D
1
A
D
B
X
X
X
C
X
X
X
C
1
X
1
X
1
C
A
D
B
A
A
C
A
X
C*
X
D
1
A
1
C
A
A*
A
X
X
X
X
A
C
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Design of Synchronous Counters (cont.)
DC
BA
D*
D
DC
BA
D
X
B
1
X
1
B
C
C
A
D
D
B
A
X
X
X
X
1
B
A
C
C
DC
BA
From the main truth table of the D*
B
JD  CBA ; KD  A
B
X
X
X
X
X
X
X
X
JD
A
A
C
C
D
D
A
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
C
A
C
KD
A
A
C
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Design of Synchronous Counters (cont.)
DC
BA
C*
D
B
B
1
X
1
X
1
1
C
DC
BA
D
C
A
D
B
A
X
X
X
X
B
1
A
C
From the main truth table of the C*
B
B
A
X
X
X
X
X
X
X
X
X
X
C
DC
BA
JC  KC  BA
D
A
A
C
C
D
D
X
X
X
A
X
X
X
A
X
X
X
X
X
1
X
C
JC
C
KC
A
C
178220 Digital Logic Design @Department of Computer Engineering KKU.
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Design of Synchronous Counters (cont.)
DC
BA
B*
B
D
DC
BA
D
A
X
1
1
X
B
1
C
1
C
B
A
X
X
X
X
B
A
C
D
D
1
1
X
X
X
X
X
X
X
X
X
C
DC
BA
From the main truth table of the C*
B
JB  DA ; KB  A
B
A
X
A
A
C
C
D
D
X
X
X
X
A
X
X
X
X
A
1
1
X
X
X
X
C
JB
C
KB
A
C
178220 Digital Logic Design @Department of Computer Engineering KKU.
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Design of Synchronous Counters (cont.)
DC
BA
A*
B
D
1
DC
BA
D
1
X
1
X
B
1
C
1
C
A
B
A
X
X
X
X
B
A
C
D
1
1
X
1
X
X
X
X
X
X
X
X
1
1
X
X
C
DC
BA
From the main truth table of the A*
B
JA  KA  1
D
B
A
A
A
C
C
D
D
X
X
X
X
A
1
1
X
1
A
1
1
X
X
X
X
X
X
C
JA
C
KA
A
C
178220 Digital Logic Design @Department of Computer Engineering KKU.
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Example: A Base-16 Counter
D
C
B
A
D*
C*
B*
A*
remark
0
0
0
0
0
0
0
1
01
0
0
0
1
0
0
1
0
12
0
0
1
0
0
0
1
1
23
0
0
1
1
0
1
0
0
34
0
1
0
0
0
1
0
1
45
0
1
0
1
0
1
1
0
56
0
1
1
0
0
1
1
1
67
0
1
1
1
1
0
0
0
78
1
0
0
0
1
0
0
1
89
1
0
0
1
1
0
1
0
9A
1
0
1
0
1
0
1
1
AB
1
0
1
1
1
1
0
0
BC
1
1
0
0
1
1
0
1
CD
1
1
0
1
1
1
1
0
DE
1
1
1
0
1
1
1
1
EF
1
1
1
1
0
0
0
0
F0
178220 Digital Logic Design @Department of Computer Engineering KKU.
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Example: A Base-16 Counter (cont.)
DC
BA
D
B
1
1
1
1
1
B
A
1
C
JD = KD = CBA
D
B
A
1
1
C
DC
BA
D
D
1
1
1
1
1
B
C
C
A
1
1
A
A
1
A
C
JC = KC = BA
178220 Digital Logic Design @Department of Computer Engineering KKU.
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Example: A Base-16 Counter (cont.)
DC
BA
B
D
DC
BA
D
A
1
1
1
1
B
D
1
D
1
1
1
A
B
A
A
B
1
C
1
1
C
1
C
JB = KB = A
A
1
1
C
1
C
1
A
C
JA = KA = 1
178220 Digital Logic Design @Department of Computer Engineering KKU.
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Example: An Up/Down Counter
X
C
B
A
C*
B*
A*
remark
0
0
0
0
0
0
1
01
0
0
0
1
0
1
0
12
0
0
1
0
0
1
1
23
0
0
1
1
1
0
0
34
0
1
0
0
1
0
1
45
0
1
0
1
1
1
0
56
0
1
1
0
1
1
1
67
0
1
1
1
0
0
0
70
1
0
0
0
1
1
1
07
1
0
0
1
0
0
0
10
1
0
1
0
0
0
1
21
1
0
1
1
0
1
0
32
1
1
0
0
0
1
1
43
1
1
0
1
1
0
0
54
1
1
1
0
1
0
1
65
1
1
1
1
1
1
0
76
JA = KA = 1
JB = KB = xA + xA
JC = KC = xBA + xBA
178220 Digital Logic Design @Department of Computer Engineering KKU.
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Example: 0, 3, 2, 4, 1, 5, 7, and repeat
q1
q2
q3
q1*
q2*
q3*
remark
0
0
0
0
1
1
03
0
0
1
1
0
1
15
0
1
0
1
0
0
24
0
1
1
0
1
0
32
1
0
0
0
0
1
41
1
0
1
1
1
1
57
1
1
0
X
X
X
6X
1
1
1
0
0
0
70
0
7
3
5
2
1
4
6
178220 Digital Logic Design @Department of Computer Engineering KKU.
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Example: 0, 3, 2, 4, 1, 5, 7, and repeat
(cont.)
178220 Digital Logic Design @Department of Computer Engineering KKU.
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Example: 0, 3, 2, 4, 1, 5, 7, and repeat
(cont.)
S1  q2 q3  q2q3
R1  q2 q3  q2q3  S1
 q2 q3  q1q2
S2  q1q2 q3  q1q2 q3
S3  q2
R2  q1q2  q2q3
R3  q2
T1  q1q2 q3  q2q3  q1q2  q1q3
T2  q1q3  q1q3
T3  q2 q3  q2q3
J1  q2 q3  q2q3
J 2  q1q3  q1q3
J3  q2
K1  q3  q2
K 2  q1  q3
K 3  q2
178220 Digital Logic Design @Department of Computer Engineering KKU.
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Design of Asynchronous Counters



Page 350….
Figure 5.31(2-bit counter)&5.32(timing delay)
Advantage:


Simplicity of the hardware  no combinational
logic required
Disadvantage:

Speed
178220 Digital Logic Design @Department of Computer Engineering KKU.
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Derivation of State tables and
State Diagrams

Consider the problem:
A system with one input x and one output z such that
z = 1 at a clock time iff x is currently 1 and was also
1 at the previous two clock times.

Another way of wording this same problem is
A Mealy system with one input x and one output z
such that z = 1 iff x has been 1 for three consecutive
clock times.
178220 Digital Logic Design @Department of Computer Engineering KKU.
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
A sample input/output trace is
x 0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 1
z 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 0 0 0



First approach:
save the previous q1
2 inputs.
0
0
Knowing them
and the present
1
input  output.
1
q2
0
1
0
1
q1*q2*
z
x=0 x=1 x=0 x=1
0 0 0 1 0
0
1 0 1 1 0
0
0 0 0 1 0
0
1 0 1 1 0
1
Just discard the older input stored in memory
and store the newer one plus the current input.
178220 Digital Logic Design @Department of Computer Engineering KKU.
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
Second approach: store in memory the
number of consecutive 1’s as follows:



A
B
C
1/0
0/0
B
one 1
none, that is, the last input was 0
one
two or more
q*
z
0/0
q
x=0 x=1 x=0 x=1
0
0
A
A
B
A no 1’s
0
0
B
A
C
0/0
C
A
C
0
1
C
1/0
two or
more 1’s
1/1
178220 Digital Logic Design @Department of Computer Engineering KKU.
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



The second approach requires only 3 states,
whereas the first requires 4. Both, however,
use 2 flip-flops.
Consider: the system produces a 1 if the
input has been 1 for 25 consecutive clock
times.
Now the first approach requires to store the
last 24 inputs and a state table of 224 rows.
The second approach requires 25 states
which can be coded with 5 flip-flops.
178220 Digital Logic Design @Department of Computer Engineering KKU.
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