Transcript Logic Gates 1 - Faculty of Engineering

Lecture 14
CMOS Logic Gates
Feb. 5, 2003
Modern VLSI Design 3e: Chapter 3
week5-1
Partly from 2002 Prentice Hall PTR
Contents of the Course
ASIC



FPGA
Transistor and Layout
Gate and Schematic
Systems and VHDL/Verilog
Modern VLSI Design 3e: Chapter 3
week5-2
Partly from 2002 Prentice Hall PTR
Contents of the Course (cont’d)
2 ASIC labs



Transistor/Layout
Gate and Schematic
Systems/VHDL
2 FPGA labs
(Cadence)
(Xilinx
Foundation)
(Synopsys)
Modern VLSI Design 3e: Chapter 3
week5-3
Partly from 2002 Prentice Hall PTR
Topics
Combinational logic functions.
 Static complementary logic gate structures.

Modern VLSI Design 3e: Chapter 3
week5-4
Partly from 2002 Prentice Hall PTR
Combinational logic expressions
Combinational logic: function value is a
combination of function arguments.
 A logic gate implements a particular logic
function.
 Both specification (logic equations) and
implementation (logic gate networks) are
written in Boolean logic.

Modern VLSI Design 3e: Chapter 3
week5-5
Partly from 2002 Prentice Hall PTR
Gate design
Why designing gates for logic functions is
non-trivial:
– may not have logic gates in the libray for all
logic expressions;
– a logic expression may map into gates that
consume a lot of area, delay, or power.
Modern VLSI Design 3e: Chapter 3
week5-6
Partly from 2002 Prentice Hall PTR
Boolean algebra terminology

Function:
f = a’b + ab’
a is a variable; a and a’ are literals.
 ab’ is a term.
 A function is irredundant if no literal can be
removed without changing its truth value.

Modern VLSI Design 3e: Chapter 3
week5-7
Partly from 2002 Prentice Hall PTR
Completeness
A set of functions f1, f2, ... is complete iff
every Boolean function can be generated by
a combination of the functions.
 NAND is a complete set; NOR is a
complete set; {AND, OR} is not complete.
 Transmission gates are not complete.
 If your set of logic gates is not complete,
you can’t design arbitrary logic.

Modern VLSI Design 3e: Chapter 3
week5-8
Partly from 2002 Prentice Hall PTR
Static complementary gates
Complementary: have complementary
pullup (p-type) and pulldown (n-type)
networks.
 Static: do not rely on stored charge.
 Simple, effective, reliable; hence
ubiquitous.

Modern VLSI Design 3e: Chapter 3
week5-9
Partly from 2002 Prentice Hall PTR
Static complementary gate
structure
Pullup and pulldown networks:
VDD
pullup
network
out
inputs
pulldown
network
VSS
Modern VLSI Design 3e: Chapter 3
week5-10
Partly from 2002 Prentice Hall PTR
Inverter
+
a
Modern VLSI Design 3e: Chapter 3
out
week5-11
Partly from 2002 Prentice Hall PTR
Inverter layout
VDD
+
a
tub ties
out transistors
a
out
(tubs not
shown)
GND
Modern VLSI Design 3e: Chapter 3
week5-12
Partly from 2002 Prentice Hall PTR
NAND gate
+
out
b
Modern VLSI Design 3e: Chapter 3
a
week5-13
Partly from 2002 Prentice Hall PTR
NAND layout
VDD
+
out
b
a
out tub
ties
b
a
GND
Modern VLSI Design 3e: Chapter 3
week5-14
Partly from 2002 Prentice Hall PTR
NOR gate
+
b
a
out
Modern VLSI Design 3e: Chapter 3
week5-15
Partly from 2002 Prentice Hall PTR
NOR layout
b
VDD
a
tub ties
b
out
out
a
GND
Modern VLSI Design 3e: Chapter 3
week5-16
Partly from 2002 Prentice Hall PTR
Pullup/pulldown network design
Pullup and pulldown networks are duals.
 To design one gate, first design one
network, then compute dual to get other
network.
 Example: design network which pulls down
when output should be 0, then find dual to
get pullup network.

Modern VLSI Design 3e: Chapter 3
week5-17
Partly from 2002 Prentice Hall PTR
Lectures 15
Transfer Characteristics
(Transfer Curve and Noise Margin)
Feb. 7, 2003
Modern VLSI Design 3e: Chapter 3
week5-18
Partly from 2002 Prentice Hall PTR
Topics

Electrical properties of static combinational
gates:
– Noise margin and transfer curve;
– delay;
– power.
Modern VLSI Design 3e: Chapter 3
week5-19
Partly from 2002 Prentice Hall PTR
Logic levels
Solid logic 0/1 defined by VSS/VDD.
 Inner bounds of logic values VL/VH are not
directly determined by circuit properties, as
in some other logic families.

VDD
logic 1
unknown
VSS
Modern VLSI Design 3e: Chapter 3
VH
VL
logic 0
week5-20
Partly from 2002 Prentice Hall PTR
Logic level matching

Levels at output of one gate must be
sufficient to drive next gate.
Modern VLSI Design 3e: Chapter 3
week5-21
Partly from 2002 Prentice Hall PTR
Transfer characteristics

Transfer curve shows static input/output
relationship—hold input voltage, measure
output voltage.
Modern VLSI Design 3e: Chapter 3
week5-22
Partly from 2002 Prentice Hall PTR
Inverter transfer curve
Modern VLSI Design 3e: Chapter 3
week5-23
Partly from 2002 Prentice Hall PTR
Logic thresholds
Choose threshold voltages at points where
slope of transfer curve = -1.
 Inverter has a high gain between VIL and
VIH points, low gain at outer regions of
transfer curve.
 Note that logic 0 and 1 regions are not equal
sized—in this case, high pullup resistance
leads to smaller logic 1 range.

Modern VLSI Design 3e: Chapter 3
week5-24
Partly from 2002 Prentice Hall PTR
Noise margin
Noise margin = voltage difference between
output of one gate and input of next. Noise
must exceed noise margin to make second
gate produce wrong output.
 In static gates, t= voltages are VDD and
VSS, so noise margins are VDD-VIH and VILVSS.

Modern VLSI Design 3e: Chapter 3
week5-25
Partly from 2002 Prentice Hall PTR
Example 1
Transfer curve and noise margin
Modern VLSI Design 3e: Chapter 3
week5-26
Partly from 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 3
week5-27
Partly from 2002 Prentice Hall PTR