Transcript UPMC / LIP6 - LSV, ENS Cachan

Timing Abstraction
Pirouz Bazargan Sabet
Patricia Renault
Dominique Le Dû
Pirouz Bazargan Sabet
ValMem - March 2010
Abstraction
Netlist Tr, C, R
Functional Abstraction
Netlist of Gates, C, R
Timing Abstraction
Gate Delays
Pirouz Bazargan Sabet
ValMem - March 2010
Functional Abstraction
follow the current paths
a
b
a
b
Fup
=b+a
Fdown = a . b
Fup = Fdown
Pirouz Bazargan Sabet
ValMem - March 2010
Functional Abstraction
Fup = db + ca
Fdown = db + ca
c
a
Fup . Fdown = c.d.(ab)
d
b
Fup + Fdown = c.d
Fup = cb+ ca
c=d
functional view  timing view
Pirouz Bazargan Sabet
ValMem - March 2010
Delay Evaluation
Accurate delay using electrical simulation
xi
y
Simulation of each configuration : 1 input
switching while others are in steady state
Pirouz Bazargan Sabet
ValMem - March 2010
Delay Evaluation
Fup = db + ca
Fdown = db + ca
c
a
d
a b c d
b
x
x
Fup = cb+ ca
Pirouz Bazargan Sabet
x
x
x
x
x
x
x
x
x
x
ValMem - March 2010
Delay Evaluation
sources of correlation
Include the gates until
reaching the sources
of correlation
 size
 some correlations are not useful
 number of configurations
Pirouz Bazargan Sabet
ValMem - March 2010
Delay Evaluation
sources of correlation
Explore the supergate to
identify the configurations
to be simulated
Functional exploration
Pirouz Bazargan Sabet
ValMem - March 2010
Delay Evaluation
Fup = db + ca
Fdown = db + ca
c
a
d
a b c d
b
x
x
Fup = cb+ ca
Pirouz Bazargan Sabet
x
x
x
x
x
x
x
x
x
x
x
x
ValMem - March 2010
Delay Evaluation
Functional correlation :
a
inputs
b
x
configs
timing correlation
transition delay between a and b depends on the
delay of the gates involved in the supergate
Electrical simulations should be
done regarding the gates’ graph
Pirouz Bazargan Sabet
ValMem - March 2010
Delay Evaluation
Timing dependency
Pirouz Bazargan Sabet
ValMem - March 2010