Transcript TileCal FE Electronics - University of Chicago

4-channel ASIC Tests
Michael Baumer, Jean-Francois Genat, Sam Meehan, Eric Oberla
August 26th 2009
-
DC, AC, Anodes tests (see also Eric’s
document)
DC tests (Chicago)
- No s/w needed
- DC power vs biases, ring oscillator frequency, ADC ramp monitoring, token passing
-
AC tests (Hawai’i)
- Chip on board (wire-bonding)
-
DACs,
FPGA,
USB interface (in the FPGA),
Fast pulser, (IEEE488 to PC)
F/w and s/w: load FPGA, program and trigger pulser, control DACs,
read digital data, manage results, (LabView ?)
Functional and parametric tests:
-
Sampling cell output vs input and sampling window
Max sampling rate, analog bandwidth
Leakages (voltage droop),
Resolution
Crosstalk
Linearities, dynamic range,
Readout speed.
- Anodes/MCP tests (Chicago)
-
4 chips (16 channels, 4”)
-
FPGA
DACs
USB
Test f/w and s/w
1
DC tests card
DC test card
Detector tests with 4-channel ASIC
Goal: Check the sampling ASIC with an actual detector
Flip-Chip
- CVInc (TX) contacted
They can do it, not clear yet if:
- Real “cheap” stud-bonding, or
- Regular “expensive” bump bonding requiring an Under Bump
Metallization
- Barcelona people will answer next week