Transcript RAMP Implementation

“Embedded” RAMP
Workshop
8/23/06
bee2.eecs.berkeley.edu/wiki/embedded
1
100-1000 Core
CMPs
RAMP Project
1M Processor
SuperComputers
1-10 Core
SoCs
2
Schedule:
10:00-10:15 Introductions, etc.
10:15-11:00 Wawrzynek, Asanovic (UCB)
RAMP Vision and Infrastructure
11:00-11:30 Uli Ramacher (Infineon)
Mass Mark Applications Driving MPSoC and Design Challenges
11:30-12:00 Ulrich Ruecker (HNI, Paderborn University)
High-level Desc. of Instructions Sets and Compi. Generation
12:00-12:30 Wolfgang Raabs (Infineon)
Virtual Prototype and Design Flow
12:30-1:30 Lunch
1:30-2:00 Kurt Keutzer (UCB)
Mapping task graphs to processors in large multiprocessor systems
2:00-2:30 Chen Chang (BEECube)
Hardware and Tools for Architecture Exploration
2:30-3:30 Free Discussion
3
RAMP Blue Prototype




8 BEE2 modules (32
“user” FPGAs)
8 100MHz.
MicroBlaze cores /
FPGA = 256 cores
Full star-connection
between modules
Diagnostics running
today, applications
(UPC) this week
4
RAMP Blue Prototype - Module in 2u Case
5