Transcript No Slide Title

Sub – 1 Ohm Broadband
Impedance Matching Network
Design Methodology for High
Power Amplifiers
W. McCalpin
dBm Engineering, Inc., Boulder, CO
July 17, 2015
dBm Engineering
5446 Conestoga Ct.
Boulder, CO 80301
dBmEngineering.com
High Power Amplifier Design Challenges
A fixed-tuned broadband 50-Ohm test fixture is
required with the following design constraints:
• Prototype RF Power Transistor: Single-Ended 250W
Pulsed LDMOS part
• The design bandwidth required is 15% (1200 to 1400 MHz)
as compared to ~ 3% for Wireless bands
• High Power Pulsed Load Pull measurements have
produced sub-1 Ohm target Load / Source impedances
(ZLoad=0.8 – j1.0) to be held nearly constant over the
bandwidth of interest
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Prototype 250W Pulsed Power LDMOS
Transistor
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Outline
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•
•
•
•
•
Motivation
Load Pull Impedance Accuracy
Proposed Simulation / Design Method
Matching Network Topology Selection
Simulation of “Ideal” Topology / Trajectory
Conversion of “Ideal” Circuit Simulation to a
Physically-based Circuit Simulation
• Fabrication of TRL Verification and DUT fixtures
• Comparison of Measured vs. Simulated
Trajectory and ZLoad
• Summary
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Motivation
Q: Why is it difficult to go from High Power Load Pull
measurements to working hardware?
Q: Why do RF Power engineers still commonly rely
heavily upon intuition, tuning and iteration?
•
Is Load Pull wrong?
The target impedances generated from doing Load Pull
may not be accurate enough to truly represent what the
DUT actually sees.
and / or
Is the simulation / design process wrong?
• Common simulation techniques may not produce
hardware that faithfully recreates the target impedances
(when the designer fabricates the physical circuit from the
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simulated circuit).
Load Pull Tuner Impedance Accuracy
(calibrated impedance vs. actual impedance during measurement)
e.g. for a ZCal point, what is the Output Tuner’s Load reflection
coefficient when ZMeas is normalized to the ZCal point
ZCal
ZMeas
ZMeas
50 Ω
ZMeas  ZCal

ZMeas  ZCal
R.L.(dB)  20log10 |  |
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Load Pull Tuner Impedance Accuracy (cont.)
Focus Microwaves - PMT
Load Pull System
*
The Tuner by itself:
50 Ω
ZMeas
Tuner
*
*
*
*
*
Tuning to the indicated points:
Worst Case R.L.(dB) meas. = ~ - 51 dB
*
Tuning repeatability:
Worst Case R.L.(dB) meas. = ~ - 47 dB
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(Based on a TRL 7/16” Connectorized VNA
calibration with Sii ≤ -60 dB)
ZLoad Impedance Accuracy at the DUT plane
The impedance presented to the DUT:
*
*
*
*
*
*
ZMeas
50 Ω
Load Pull
Test Fixture
Tuner
Tuning to the indicated points:
Worst Case R.L.(dB) meas. = ~ - 31 dB
*
Tuning repeatability:
Worst Case R.L.(dB) meas. = ~ - 31 dB
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(Based on a TRL Impedance Transforming PCB
VNA calibration with Sii ≤ -41 dB)
Load Pull Tuner Impedance Accuracy (cont.)
• Given the proper discipline in
calibration and setup, the accuracy of the
Load Pull targets is very good
• Load Pull targets should be useful for
design as well as device characterization
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Proposed Simulation / Design Method
•
•
•
•
•
Ideal impedance matching network topology /
trajectory simulation (using circuit models and
lumped elements)
Identification of the circuit response to tuning
variations
Conversion of distributed elements to EM based
multi-port S-parameter blocks
Conversion of lumped element models to measured
one-port and two-port S-parameter blocks
Simulation refinement and design centering
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Proposed Simulation / Design Method
(cont.)
•
•
•
•
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Design and fabrication of a TRL verification fixture
and the break-apart DUT impedance matching
fixture
Assembly of each half of the DUT fixture with
component by component verification of the
impedance matching trajectory using the TRL
verification fixture
Full DUT fixture assembly
Top-level tuning and design centering
Break-apart measurement of the final Load and
Source impedances.
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Ideal Topology / Trajectory Simulation
Output
Matching
Network
Z0 = 4.48 Ohms
50 Ohms
Load Matching Network: Two-section Low-Pass with ideal elements
SRLC
SRLC26
Term
Term16
Num=16
Z=50 Ohm
MLIN
TL43
MLIN
TL42
SRLC
SRLC25
SRLC
SRLC33
MLIN
TL41
SRLC
SRLC32
SRLC
SRLC27
MLIN
TL40
SRLC
SRLC28
MLIN
TL39
MLIN
TL38
SRLC
SRLC30
MLIN
TL37
SRLC
SRLC31
SRLC
SRLC29
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Section 2
MLIN
TL36
Section 1
R
R2
R=50 Ohm
Conversion of Distributed Elements to EM
based Simulation (using Momentum)
Generates a 13 port .s13p file to import into ADS to
with the measured .s1p files of the components
Julycombine
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Conversion of Lumped element circuit
models to measured s1p and s2p files
• Measured using 50-Ohm TRL standards either wafer-probed
(preferred) or connectorized (as shown)
• Using the application substrate and component mounting
configuration to include all substrate parasitic effects
• Commercially available Model Libraries are ideal – parameterized to
substrate material, full range of values by product type, accurate and
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wideband to include harmonic frequencies, etc.
Design and Fabrication of a Break-Apart
DUT Impedance Matching Fixture
ZLoad
Fabricated to be Break-apart using the substrate selected for
the application
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Design and Fabrication of an Impedance
Transforming TRL Verification Test Fixture
Fabricated on the substrate to be used in the application with
July a
17, line
2015 width equal to the lead width of the DUT (500 mils)
Measurement of the DUT Break-apart fixture
using the TRL Verification fixture
ZLoad
After TRL calibration using the Verification fixture, multiple
measurements
can be made as each lumped component is
July
17, 2015
added
''C:\ADS\GHz\3_block_output_prj\data\PA_paper_MOM_Output_8.ds''..S(1,1)
PA_paper_MOM_Output_4..S(1,1)
PA_paper_MOM_Output_3..S(1,1)
''C:\ADS\GHz\3_block_output_prj\data\PA_paper_MOM_Output_2.ds''..S(1,1)
PA_paper_MOM_Output_4..S(1,1)
PA_paper_MOM_Output_5..S(1,1)
PA_paper_MOM_Output_3..S(1,1)
''C:\ADS\GHz\3_block_output_prj\data\PA_paper_MOM_Output_6.ds''..S(1,1)
''C:\ADS\GHz\3_block_output_prj\data\PA_paper_MOM_Output_2.ds''..S(1,1)
PA_paper_MOM_Output_4..S(1,1)
PA_paper_MOM_Output_5..S(1,1)
PA_paper_MOM_Output_3..S(1,1)
S(10,10)
''C:\ADS\GHz\3_block_output_prj\data\PA_paper_MOM_Output_2.ds''..S(1,1)
PA_paper_MOM_Output_13..S(11,11)
PA_paper_MOM_Output_3..S(1,1)
S(9,9)
''C:\ADS\GHz\3_block_output_prj\data\PA_paper_MOM_Output_2.ds''..S(1,1)
PA_paper_MOM_Output_12..S(11,11)
S(8,8)
''C:\ADS\GHz\3_block_output_prj\data\PA_paper_MOM_Output_2.ds''..S(1,1)
PA_paper_MOM_Output_11..S(11,11)
PA_paper_MOM_Output_13..S(11,11)
S(7,7)
PA_paper_MOM_Output_10..S(11,11)
PA_paper_MOM_Output_12..S(11,11)
PA_paper_MOM_Output_13..S(11,11)
S(6,6)
PA_paper_MOM_Output_13..S(13,13)
PA_paper_MOM_Output_9..S(10,10)
PA_paper_MOM_Output_11..S(11,11)
PA_paper_MOM_Output_12..S(11,11)
PA_paper_MOM_Output_13..S(11,11)
S(5,5)
S(4,4)
PA_paper_MOM_Output_13..S(11,11)
PA_paper_MOM_Output_9..S(1,1)
PA_paper_MOM_Output_10..S(11,11)
PA_paper_MOM_Output_11..S(11,11)
PA_paper_MOM_Output_12..S(11,11)
PA_paper_MOM_Output_13..S(11,11)
S(1,1)
S(5,5)
S(4,4)
S(4,4)
S(1,1)
S(4,4)
Simulated vs. Measured ZLoad Impedance Trajectory
Term
Term16
Num=16
Z=50 Ohm
MLIN
TL43
Chart Zo = 4.48 Ohms
Target Load Impedance = 0.8 - j1.0
freq
freq
freq
freq
(1.200GHz
(1.200GHz
(1.200GHz
(1.200GHz
toto
to
1.400GHz)
to
1.400GHz)
1.400GHz)
1.400GHz)
freq
(1.200GHz
to
1.400GHz)
freq
freq(1.100GHz
(1.100GHztoto1.500GHz)
1.500GHz)
Load Matching Network: Two-section Low-Pass with ideal elements
SRLC
SRLC26
MLIN
TL42
SRLC
SRLC25
SRLC
SRLC33
MLIN
TL41
SRLC
SRLC32
Section 2
SRLC
SRLC27
MLIN
TL40
SRLC
SRLC28
MLIN
TL39
MLIN
TL38
SRLC
SRLC30
MLIN
TL37
SRLC
SRLC31
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Section 1
MLIN
TL36
SRLC
SRLC29
R
R2
R=50 Ohm
Pulsed P1dB, Efficiency and Gain vs.
Frequency
60.00
14
59.00
13
Gain at P1dB
58.00
57.00
56.00
11
Eff. at P1dB
10
55.00
54.00
12
9
P1dB
Pout vs Freq
Eff. at P1dB
Gain at P1dB
53.00
8
7
52.00
6
51.00
5
50.00
1200
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1250
1300
Frequency (MHz)
1350
4
1400
Gain at P1dB (dB)
P1dB (dBm) and Drain Eff.
at P1dB (%)
Test conditions: Vdd=32V, Idq = 500 mA (pulsed), Pulse width = 6mS, Duty Cycle = 25%
Summary
Invest in your Methodology!
• High Power Load Pull is useful for design as well as
characterization
• Choose a topology that will hit the required impedance
targets and achieve the desired matching network
trajectory
• Replace the ideal circuit elements with EM and
measurement based elements as early as possible
• Verify each simulated step by measuring at every step
• Know the impacts of tuning locations and keep them
small
• Center and finalize the tuning and
measure the final impedances
• Improve the process
July 17, 2015
References
[1] D. Williams and D. Walker, “On-Wafer Measurement Accuracy”,
ARFTG Short Course on Measurements and Metrology for RF
Telecommunications, November 2000
[2] http://www.boulder.nist.gov/micro
July 17, 2015