Transcript Broadband Data Signals & Circuits

Shunt-Peaking (1)
By connecting an inductor in series with the load
resistor (series connection in shunt with output),
more current is used, for a longer time, to charge
the load capacitance.
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine
1
Properties of Shunt-Peaking
Frequency response:
L
R
Z( j )  R 
2
1  LCL  jCL R
1 j
CL
L
R
Z(s)  R 
1 sCL R  s 2LCL


1 s

Resonant frequency:
1  CL R2 
r 
1

LCL 
L 
2
Im s

X
OX
Re s
L = 0:
L ≠ 0:
zero at s = −R/L pole at s = −1/RC
additional pole at
s ≈ −(1/CR + R/L)
EECS 270C / Winter 2013

Prof. M. Green / U.C. Irvine
L
1
No resonance for
2
CL R

2
Shunt-Peaking -- AC Response
L
 0.3
CL R 2
CL  38 fF
L = 1.8 nH
BW = 9.4 GHz
R = 400 


Use of shunt-peaking
increases small-signal bandwidth

EECS 270C / Winter 2013
L
 0.6
CL R 2
L0
BW = 6.3 GHz
L = 3.7 nH
BW = 14.3 GHz

Prof. M. Green / U.C. Irvine
3
Shunt Peaking − Transient Response (1)
Step Response:
Pulse Response (Dtin = 50 ps):
L = 3.7 nH
Dtout = 50.8 ps
ISI = 16 mUI
L = 3.7 nH
td = 6.7 ps
L = 1.8 nH
td = 8.5 ps
L0
td = 13.4 ps
L = 1.8 nH
Dtout = 50.0 ps
ISI = 0 mUI
L=0
Dtout = 48.7 ps
ISI = 26 mUI

EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine
4
Other Advantages of Shunt-Peaking
• CML load is passive & linear
• Can be shown to be very robust in the presence of parasitic
series resistance and shunt capacitance  inductors can be
placed far away from other CML circuit elements.
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine
5
Effect of Shunt-Peaking Inductor Parasitics (1)
L
L
L
CP
CP
L
long metal lines
RP
R
R
CL
CL
RP
R
R
CL
CL
• Series resistance RP simply adds to R
• Shunt capacitance CP resonates with L …
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine
6
Effect of Shunt-Peaking Inductor Parasitics (2)
L
 0.6
CL R 2
ISI (UI) vs. input pulse width
CP  0

L
0
CL R 2

Moderate amount of parasitic capacitance
has similar effect to slightly larger inductor.


L
 0.6
CL R 2
ISI (UI) vs. input pulse width
CP  0.2CL

Disadvantages of using passive inductors:
• Consume huge die area
• Difficult to design & model
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine
L
 0.3
CL R 2

L
0
CL R 2
L
 0.3
CL R 2


7
Multi-layer Inductors (1)
metal 6
metal 6
d
metal 5
metal 5
d
Distance d between two metal layers is much smaller than lateral distances
(e.g., w, l, s)
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine
8
Multi-layer Inductors (2)
2-port representation of coupled inductors:
M  k L1L2
i1
+
1
series connection of coupled inductors:
i1
i2

L1
L2
_
M
+
+
1 L1
2
L2 2
_
_
_
+
Passivity constraint: k  1
i2
series       (L1  M)i 1  (L2  M)i 2
  L M i 
1
    1
 
   M L2 i 2 
i series  i   i 

For metal geometries close to each other, 
k is close to unity.

Lseries 
series
i series
 L1  L2  2M

For L1 = L2 = L, we have: Lseries  2L  2M  2L(1 k)  4L
2
In general, for n layers we have: Lseries  n L


Multi-layer inductors are more appropriate for shunt-peaking than resonant structures
due to additional
contact resistance.
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine

9
Multi-layer Inductors (3)
Effective Capacitance:
Leffective  4L
Ci
1
1
Ceffective  Ci  Cj
3
12

Cj

For more details, see:
A. Zolfaghari, A. Chan & B. Razavi, “Stacked inductors and transformers in
CMOS technology,”
IEEE Journal of Solid-State Circuits, vol. 36, April 2001, pp. 620-628.
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine
10
Multi-layer Inductors (4)
Area comparison:
metal 6 only
100 x 100
w = 4; s = 2; n = 4
L=2.0 nH
R=6.9 
metal 6 over metal 4
46 x 46
w = 4; s = 2; n = 2.5
L=2.0 nH
R=12.5 
+
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine
11
Active Inductors (1)
Impedance inversion:
Ideal gyrator:
i1
Rgyr
i2
iin
+
+
+
v1
v2
vin
_
_
_
v 2  Rgyr i1
 
Matrix representation (Z-parameters):
EECS 270C / Winter 2013
Rgyr i1 
 
0 i 2 
C
2
Zin  Rgyr
sC
v1  Rgyr i 2
v   0
  1  
v 2  Rgyr
Rgyr
Port 1 exhibits inductance when
port 2 is connected to a capacitance.

Prof. M. Green / U.C. Irvine
12
Active Inductors (2)
Consider common-drain configuration:
i1 applied with port 2 open-circuited:
v2 
i2
RG
1
i1
gm
i2 applied with port 1 open-circuited:
+
v2

_
_

1 
v1  RG  i 2
gm 

(Assume RG gm > 1)
v1
i1
+

EECS 270C / Winter 2013
Complete Z-parameters (lossy/active gyrator):

v  1 g  R 1 g
G
m
 1   m
1 gm
v 2  
1 gm
Prof. M. Green / U.C. Irvine
i 
1

i 2 
13
Active Inductors (3)
Interpretation of non-ideal matrix entries:
+
v  1 g 1 g  R i 
m
G
1
 1   m
 
1 gm i 2 
v 2  1 gm
vin

_
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine
14
Active Inductors (4)
Impedance at port 1 with port 2 terminated with transistor Cgs:
At low frequencies (Cgs open)  Zsource = 1/gm
At high frequencies (Cgs short)  Zsource = RG
Zsource

EECS 270C / Winter 2013
1 1 sCgs RG 



gm 1 s Cgs gm 
Prof. M. Green / U.C. Irvine
15
Active Inductors (5)
Equivalent circuit:
Leff 
Zsource
Cgs RG RG

gm
T
RG
1
gm
+


vin
1
gm
gm
Cgs
1
Cgs RG

gmRG  1


EECS 270C / Winter 2013


Cgs 

_
RG
gm
RG 
1
gm



Prof. M. Green / U.C. Irvine
16

CML Buffer with Active Inductor Load
Low-frequency gain:
Av 
gm 1
W1

gm 2
W2
For shunt peaking:

L  0.3CL R2

W 
4
  
 L 1 0.18
W 
2.5
  
 L 2 0.18
ISS  400 A

EECS 270C / Winter 2013
Cgs RG
C
 0.3 2L
gm 2
gm 2

gm 2RG  0.3
CL
Cgs

Prof. M. Green / U.C. Irvine
17
Active Inductor AC Response
RG = 4k
RG = 2k
RG = 0
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine
18
Active Inductor Transient Response (1)
Differential signals:
RG = 0
PW = 97ps
RG = 5k
PW = 100 ps
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine
RG = 10k
PW = 104 ps
19
Active Inductor Transient Response (2)
Single-ended signals:
Problem: n-channel load shifts output by Vt.
Vsb > 0; body effects exacerbates this effect..
Single-ended
input
Single-ended
outputs
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine
20
Active Inductor Alternate Topology
Alternate topology:
p-channel load exhibits lower Vt
(Vbs = 0)
differential
single-ended
EECS 270C / Winter 2013
Prof. M. Green / U.C. Irvine
21