Transcript Slide 1
Design of Sub-mW RF CMOS
Low-Noise Amplifiers
Derek Ho
Dept. of Electrical and Computer Engineering
University of British Columbia
March 30, 2007
Outline
Motivation and Objectives
Device Characteristics
Design Methodology
90nm 2.4GHz LNA Design and Results
Conclusion and Future Work
2
Introduction
What is an LNA?
A circuit used to provide gain where preserving
the signal-to-noise ratio is important
Where can I find one?
In wireless/wireline receivers and sensor
interfaces
Why ultra-low-power?
Want a long battery life for portable/remote
applications and implants
3
LNA Requirements
Receive Chain
1
2
3
4
VDD
Ld
VB
Lg
RFin
Ctune
M2
RFout
M1
Cm
Ls
Noise figure of receiver (F = noise figure, G = gain):
Ideally low
(for data rate and range)
4
LNA Requirements
Output
Ideal
Better Linearity
Worse Linearity
Input
An LNA with good linearity can handle a larger
input signal without deviating from linear operation.
5
LNA Design Challenges
Tightly Coupled
Performance
Tradeoff
Lack of
Systematic
Analog Design
Technique
Complex Simulation
(Noise/Nonlinearity)
Stringent Power
and Area
Requirement
Low-Q On-chip
Inductors
LNA Design
Complex
MOSFET
Models
Shrinking Supply
Voltage
MOSFET Low
Output Resistance
6
Research Objectives
Devise a simple methodology that leads to
power-efficient LNA designs
- Form a graphical toolkit to help reduce design time and improve design quality
- Explore LNA power-performance tradeoffs
- Find a low-voltage low-power circuit topology
- Demonstrate a high performance design in a deep submicron technology
7
Outline
Motivation and Objectives
Device Characteristics
Design Methodology
90nm 2.4GHz LNA Design and Results
Conclusion and Future Work
8
Gain and Transconductance
Advantage of graphical approach: Quicker, more accurate
“gain / frequency response vs. bias”
“gain vs. bias”
50
0.4
0.6
40/0.2
35
30
25
20
15
10
5
(40/0.2)
0
strong inversion
100
40/0.1
40
subthreshold
150
20/0.1
45
ggm
[mS]
m [mS]
subthreshold
f [GHz]
Transit
T Freq. (GHz)
40/0.2
(20/0.1), (40/0.1)
strong inversion
40/0.1
200
moderate inversion
20/0.1
moderate inversion
50
250
0
0
0.2
VGS [V]
VGS [V]
0.8
1
0
0.2
0.4
0.6
0.8
1
VGS [V]
VGS [V]
Both fT and gm are strong functions of VGS
fT a strong function of L, but largely independent of W
MOSFET has poor subthreshold performance
9
Transconductance Efficiency gm/ID
35
15
10
5
40/0.1
strong inversion
20
20/0.1
moderate inversion
25
subthreshold
gmgm/ID
/ID [1/V]
[1/V]
30
40/0.2
0
0
0.2
0.4
0.6
0.8
1
VGS (V)
VGS [V]
First proposed in 1996 for op-amp (low-frequency) design [1]
Represents “gain achieved” per unit “power consumed”
Decreases towards strong inversion
Insensitive to W and L
can first design VGS (bias) then design W (size)
10
moderate
inversion
Linearity
subthreshold
strong inversion
VGS [V]
VIP3 of a 40nm nFET vs. VGS (VTH = 0.23V) [22]
VIP3 (measure of linearity, the greater the better) is the highest at
moderate inversion (around 0.25V for the 45nm FET).
11
Outline
Motivation and Objectives
Device Characteristics
Design Methodology
90nm 2.4GHz LNA Design and Results
Conclusion and Future Work
12
Circuit Topology
Cascode
Common-Source
VDD
VDD
Ld
Ld
RFin
Ctune
RFout
Lg
M1
Cm
Ctune
Ls
Problems with common-source
- Low device output resistance low gain
- Poor input/output isolation Instability
RFin
VB
Lg
M2
RFout
M1
Cm
Ls
Cascode Design:
Lg, Ls, Ld, Cm, Ctune,
VB, VGS1, W1/L1, W2/L2
13
Transistor Sizing for Noise
10
Cascode NF
9
CS NF
8
NFLNA
[dB]
NF [dB]
7
Cascode
Common-Source
6
5
4
3
2
1
0
0
20
40
60
80
100
120
[μm]
WW [μm]
NF of LNA improves with larger W
However, power proportional to W
Noise-power tradeoff
14
Design Procedure
Step 1: Choose the bias VGS
Selection criteria:
2)
3)
Tradeoff gm (gain) and gm/ID (power)
For noise, want low VGS for a large
W but avoid subthreshold operation
For linearity, exploit high VIP3
50
20/0.1
45
40/0.1
40
40/0.2
35
gm [mS]
1)
Design Sweet Spot
30
25
20
15
gm
10
5
0
0
0.2
0.4
0.6
0.8
1
VGS [V]
35
20/0.1
30
40/0.1
40/0.2
Bias the device in moderate inversion
gm/ID [1/V]
25
gm/ID
20
15
10
5
0
0
0.2
0.4
0.6
0.8
1
VGS (V)
15
Design Procedure
Step 2: Calculate ID
ID = (Power) / (Supply voltage)
Step 3: Transistor Sizing (Find W)
(VGS VTH ) 2
I D Wv sat Cox
(1 VDS )
(VGS VTH ) Ec L
Step 4: Find gm
gm=d(ID)/d(VGS), or by simulation
16
Design Procedure
Step 5: Determine gate-source cap Cgs
Decide whether adding Cm is beneficial Cm decreases
fT but alleviate the need to build large inductors
VDD
Ld
VB
Lg
RFin
Ctune
M2
RFout
M1
Cm
Ls
Cgs = Cm || Cgs1
17
Design Procedure
Step 6: Impedance matching
Design Lg, Ls, & Cm to create a 50Ω input impedance.
Small-signal model
g L
1
Z in
j ( Ls L g ) m s
jC gs
C gs
Zin
Lg
Rs
Cm
Cgs1
υRF
e{Z in }
gmVgs
Ls
g m Ls
Rs 50
C gs
VDD
Ld
m{Z in }
+
Vgs
-
1
( Ls L g ) 0
C gs
VB
Lg
RFin
Ctune
M2
RFout
M1
Cm
Ls
Designing
18
Design Procedure
Step 7: Design the load Ld and Ctune
Ld, Ctune and the parasitic caps at the output
should resonate at the frequency of
operation
Designing
VDD
Ld is often chosen as large as it can
practically be implemented to increase gain
Ld
VB
Lg
RFin
Ctune
M2
RFout
M1
Cm
Ls
19
Outline
Motivation and Objectives
Device Characteristics
Design Methodology
90nm 2.4GHz LNA Design and Results
Conclusion and Future Work
20
A 90nm 2.4GHz LNA
VDD
Ld
VB
Lg
RFin
Ctune
M2
RFout
M1
Cm
Ls
Cascode with on-chip inductors
1V supply can share with digital
We now proceed to LNA (circuit-level) design…
21
Gain
“gain vs. size”
“gain vs. bias”
25
Subthreshold Region
25
21
20
23
22
v
22
24
AvA[dB]
[dB]
23
v
AvA [dB]
[dB]
24
Power
19
21
20
Power
19
18
18
0.3
0.4
0.5
0.6
0.7
VGS [V]
VGS [V]
Gain insensitive to VGS
10
15
20
25
30
35
40
W [μm]
W [μm]
Gain does not scale well with W
22
NF vs. f (sweeping VGS)
10
Noise
9
Noise Summary
0.
3V
G
S=
7
6
V
NF [dB]
8
5
Power
Increase
4
3
2
Top 5 Noise Contributors:
1 (9.2%)
2 (8.6%)
3 (8.2%)
Ctune
4 (7.3%)
noise 5 (5.5%)
Rsrc
1
1.5
2
2.5
3.5
3
f [GHz]
4
Ld
3
VGS 0.4-0.7V: -0.6dB at 6.4x power
NF vs. f (sweeping W)
10
Lg
9
8
2
7
Power
Increase
6
5
4
3
Meaning: Need to make inductors
with low series resistance!
0μ
5
m
1
W
=1
(52%)
1
NF [dB]
40% of total
(76% of which
comes from the R’s
in the inductors)
.4 V
=0
V GS 0.5V
=
V GS
0.6V
=
V GS .7V
0
V GS=
μm
20
=
W μm
30
W=
0μm
W=4
2
1
1
1.5
2
2.5
3
3.5
f [GHz]
W 10-40μW: -3.4dB at 4.2x power
23
Linearity
“LNA linearity vs. bias”
8
Power
IIP3
[dBm]
IIP3 [dBm]
6
4
Adjusted W
2
0
Constant W
-2
-4
0.4
0.45
0.5
0.55
0.6
0.65
0.7
GS [V]
VVGS
[V]
40nm
Linkage between LNA performance
and device characteristic
24
Simulation Results
2.4 GHz
TABLE 2
Summary of LNA Performance
25
5
20
4.5
15
4
10
3.5
5
3
0
2.5
1.5
2
2.5
f [GHz]
3
3.5
NF [dB]
Av [dB]
Gain: 22.7dB
Gain (dB)
22.7
NF (dB)
2.8
S11 (dB)
−14.7
IIP3 (dBm)
5.14
P1dB (dBm)
−10
PDC (μW)
943
fc (GHz)
2.4
Gate L (μm)
0.09
Power: 943μW
Noise: 2.8dB
25
Component Values
VDD
Ld
RFin
VB
Lg
Ctune
M2
M1
Cm
Ls
RFout
VDD (V)
1
Lg = Ld (nH)
5
Ls (nH)
2
Cm (fF)
480
Ctune (fF)
720
W1/L1 (μm)
25/0.1
W2/L2 (μm)
25/0.1
Vin,DC (V)
0.4
VB (V)
0.9
All components can be conveniently implemented on-chip!
26
Performance Comparison
< 1mW
> 1mW
30
Best
Gain (dB)
25
This Thesis
> 1mW
20
[15], ‘05
15
[14], ‘06
[12], ‘06
[13], ‘05
10
[8], ‘05
[9], ‘06
[10], ‘05
< 1mW
[11], ‘04
5
Worse
0
0
1
2
3
4
5
Noise Figure (dB)
This work (simulated) vs. others (measured)
This work focuses on design methodology
Highest gain amongst all LNAs
Good noise figure amongst sub-mW LNAs
27
Outline
Motivation and Objectives
Device Characteristics
Design Methodology
90nm 2.4GHz LNA Design and Results
Conclusion and Future Work
28
Conclusion
A design methodology was devised for sub-mW RF
CMOS LNAs having the following benefits:
1) simple to apply
2) can serve as a starting point for local optimization
3) based on the fundamental device properties
The gm/ID approached previously used for low-frequency
op-amp design was adopted for radio-frequency design
A 2.4GHz 943μW LNA was designed with only manual
design optimization
29
Future Work
Enhancements to the proposed methodology:
Incorporate a quantitative noise analysis into the gm/ID
design framework
Account for process variation and DFM concepts
Silicon verification
Interesting/high-impact research areas:
Noise optimization technique for the ultra-low-power
design space
Further exploitation of high FET linearity in moderate
inversion
30
Related Publications
1.
2.
D. Ho and S. Mirabbasi, “Design considerations for
Sub-mW CMOS RF low-noise amplifiers,” to appear
in IEEE Canadian Conference on Electrical and
Computer Engineering, 2007.
D. Ho and S. Mirabbasi, “Low-voltage low-power
low-noise amplifier for wireless sensor networks,”
IEEE Canadian Conference on Electrical and
Computer Engineering, 2006.
31
References
[1]
[2]
[3]
[22]
[28]
[29]
[30]
[31]
[32]
[33]
F. Silveira, D. Flandre, and P. G. A. Jespers, “A gm/ID based methodology for the design of CMOS analog
circuits and its application to the synthesis of a silicon-on-insulator micropower OTA,” IEEE J. Solid-State
Circuits, vol. 31, no. 9, Sep. 1996.
T.-K. Nguyen, S.-K. Han, and S.-G. Lee, “Ultra-low-power 2.4GHz image-rejection low-noise amplifier,”
Electronics Letters, vol. 41, no. 15, July 2005.
D. B. G. Perumana, S. Chakraborty, C.-H. Lee, and J. Laskar, “A fully monolithic 260-μW, 1-GHz subthreshold
low noise amplifier,” IEEE Microwave and Wireless Components Letters, vol. 15, no. 6, Jun 2005.
Ming Cai, “Design studies of nanometer-gate low-noise amplifier near the limits of CMOS scaling,” Doctor of
Philosophy Thesis, University of California, San Diego, San Diego, CA, 2006.
S. B. T. Wang, A. M. Niknejad, and R. W. Brodersen, “Design of a sub-mW 960-MHz UWB CMOS LNA,” IEEE
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D. Linten, L. Aspemyr, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Thijs, R. Garcia, H. Jacobsson, P.
Wambacq, S. Donnay, and S. Decoutere, “Low-power 5 GHz LNA and VCO in 90nm RF CMOS,” IEEE Sym.
on VLSI Circuits, June 2004.
S. Asgaran, M. J. Deen, and C.-H. Chen, “A 4-mW monolithic CMOS LNA at 5.7GHz with the gate resistance
used for input matching,” IEEE Microwave and Wireless Components Letters, vol. 16, no. 4, Apr. 2006.
L.-H. Lu, H.-H. Hsieh, and Y.-S. Wang, “A compact 2.4/5.2-GHz CMOS dual-band low-noise amplifier,” IEEE
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T.-S. Kim and B.-S. Kim, “Post-linearization of cascode CMOS low noise amplifier using folded PMOS IMD
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32
Thank you!
33
Appendices
34
I-V Characteristics (90nm nFET)
6
VGS = 0.7V
30
20/0.1
5
40/0.1
25
1mW
40/0.2
4
ID [mA]
ID [mA]
20
15
3
10
2
5
1
0
VGS = 0.6V
0.5mW
VGS = 0.5V
0.1mW
VGS = 0.4V
VGS = 0.3V
0
0
0.2
0.4
0.6
0.8
1
0
0.2
VGS (V)
0.4
0.6
0.8
1
VDS [V]
ID scales with W, ID does not scale with 1/L
Bias selection with constant power contours
35
Characteristic Current Densities
S.P. Voinigescu, T.O. Dickson, T. Chalvatzis1, A. Hazneci, E. Laskin, R.
Beerkens, and I. Khalid, “Algorithmic Design Methodologies and Design
Porting of Wireline Transceiver IC Building Blocks Between Technology
Nodes,” CICC, San Diego, Sept.19, 2005.
36
Drain Current Modeling
90nm FET
Square Law
DSM
Actual
37
Linearity – IP3
Intermodulation Distortion
By Quasi Periodic Steady State (QPSS) Analysis
38
Dynamic Range – P1dB
1dB compression point by Periodic Steady State (PSS) Analysis
39