Transcript Master figure – ch. 2 - Georgia Institute of Technology

CHAPTER 2
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Master Figure
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig 2.1
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig. 2.2
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig. 2.3
Lower Cost
Application
Specific
Requirements –
EMI, SER, …
Lower Power
Dissipation
Customer
Form
Factor
Requirements
Programmability
Ease of
development
and debug
Time to Market
Performance
Headroom
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig. 2.4
Accelerator
RISC
DSP
IMX
Viterbi
TurboCoding
Motion Est
:
Memory
Memory Cntrl
EMIF
DDR
:
Analog IP
ADC/DAC
PLL
Pwr Mgmt
:
Interface
Ethernet
USB 1.x/2.x
1394 a/b
PCI
PCI Express
Utopia
SERDES
UART
I2C
:
Ap Specific
Customer IP
:
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig. 2.5
Connectivity
Bluetooth
GPS
UWB
TV
Audio
GSM
Imaging
GPRS
Video
EDGE
Games
CDMA
PDA
UMTS
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Communications
Applications
802.11
Fig. 2.6
2 Ch ADC
PCM1804
CPU
X4 PLL
OSC
FPGA
Conversion
&
Clock Gen
DAC – 8
Ch
4
PCM1738
SPDIF XMIT
DIT
Otpo
TX
EMIF
Micro Controller
RAM
ROM
Eliminate 7 ICs
2 Ch ADC
PCM1804
DA610-225Mhz
McASP
SPDIF
RCV
DIR1703
Osc
&
PLL
XTAL
CPU
RAM
ROM
McASP
XTAL
C6711-150 MHz
McBSP
SPDIF
RCV
DIR1703
McBSP
XTA
L
DAC – 8 Ch
Reduce BOM
4 PCM1738
Reduce Manf. Cost
Otpo
TX
Single Processor
Sys
Reduce Time to
Market
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig. 2.7
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig. 2.8
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig. 2.9
HW/SW
Applications
Product
Engineering
EDA Tools/
Design Flows
SW Dev and
Debug Tools
SoC Design
Soft and
Hard IP
Create
Packaging
Silicon
Technology
Development
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig. 2.10
PGM MEM CNTRL
L1P
DMA
CPU
L2
DMA
L1D
DATA MEM CTRL
DMA
I/F ENGINE
EMIF
OFF-CHIP MEMORY
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig. 2.11a
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig. 2.11b
Lid/mold compound
Lid attach
Die
epoxy
Underfill
Substrate
BGA
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig. 2.12a
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig. 2.12b
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig 2.13
Design Constraints
F
HW Requirements
HW Architecture
Custom
Logic
Functional simulation
Chip-level Integration
K
Synthesis
Bridges
Drivers
Functional Verification
FVEC (RTL-Gates)
DFT
ATPG
Application
specific
module
in C /
Assembly
Subsystem-level
STA (Wire load)
Floorplanning
Chip-level
Place & GRoute
Tech Libraries
Simulation
Custom
Logic
Subsystem
Integration
C/Assembly
Coding
SW Integration
Compile code for
target processor
Verification
Profiling and
Optimization
Synthesis
CTS & DRoute
Formal Verification
FVEC (Gates-Gates)
SDF Generation / STA
Regression
DFT
Physical Design
Regression
PG
HW/SW Integration & Test
PRODUCT
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Gate-level / SPICE
HW-SW Cosimulation
- SW coSimulation
FVEC (Gates-Gates)
SDF Generation / STA
Reusable
modules
RTL / ISS HW
- SW coSimulation
A
C
Subsystem
Integration
SW Architecture
SW
Processor/
DSP cores
Memories
Peripherals
Controllers
Functional /
Behavioral
RTL Coding
HW
Reusable
modules
HW/SW
Co-simulation
B
SW Requirements
IP Repository
E
D
System Architecture Design
HW/SW Partitioning & tradeoffs
SIMULATION / VERIFICATION
E
Executable SystemLevel
Spec.
Requirements & Specifications
Fig 2.14
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig 2.15
eXpressDSP Software
Customer Application
Reference Frameworks
Code Composer Studio (CCS)
TMS320
Algorithm Standard
(XDAIS)
Compilers, LinkersRTDX
Simulators
Assemblers
co-designed
Real-Time
Debuggers
Build
with TI DSPs Analysis
Emulators
Simulators
Debugge
Debuggers
r
Emulators
Simulators
Debuggers
Simulation
Plug-Ins
Emulators
Debug
RTDX
RealReal-Time
Time
Analysis
Analysis
DSP/BIOS
RTDX
Real-Time
Plug-insCompliant
Plug-Ins
Analysis
XDS510 Emulator
XDS510 Emulator
or
or Simulator
Simulator
PC Host Computer
CSL
JTAG
JTAG
RTDX
RTDX
DSP/
BIOS
Drivers
On-Chip Emulation Support
TMS320TM DSP Target
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig 2.16
Pitch (nm)
Aspect Ratio
800
4.0
600
3.0
400
2.0
200
1.0
0
0.0
1997
2001
2006
2009
2012
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig 2.17
40-50% is leakage
power
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig 2.18
Source: Control Engineering with data from Advanced Micro Devices, Inc.
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
(M)
Fig 2.19
10,000
10,000,000
100,000
100,000,000
Logic Tr./Chip
10,000
10,000,000
Tr./Staff Month.
100
100,000
Productivity
(K) Trans./Staff - Mo.
Logic Transistor per Chip
1,000
1,000,000
58%/Yr. compounded
Complexity growth rate
10,00010
100
100,000
1,0001
10
10,000
x
0.1
100
xx
x x
0.01
10
x
1
1,000
21%/Yr. compound
Productivity growth rate
x
x
0.1
100
0.01
10
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
1987
1985
1983
0.001
1
1981
Complexity
1,000
1,000,000
Source: Sematech
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig 2.20
Specification-level
Influences functionality, cost, etc.
System-level
Module-level
Architecture-level representation
Defines the blocks, IP
+
Logic-level
Register Transfer-Level representation
Synthesizes gates, registers
Circuit-level
Transistor representation
Tunes the performance, power, etc.
G
Device-level
S
n
+
D
n
+
Layout representation
Influences the parasitics, and hence
device operation
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig 2.21
•Time to Market
•Multi-million Gates
•IP / Component Re-use
•Divide & Conquer
•Large design database sizes
•High performance
•High Density
Abstraction
•Higher Parasitics
•Interconnect delay
•Higher Cross-coupling
•Power
•Electro-migration
•IR drop
•Package careabouts
Accuracy
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig 2.22
Increased Run-times
Implementation
&
Closure
Planning
Early & Incomplete Data
Quick Iterations
“Coarse”
Optimizations
Commit Decisions
Complete Data
Costly Iterations
“Detailed”
Optimizations
Increased Accuracy
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig 2.23
IP-1
IP-2
...
Hierarchical SoC
Design Planning
Partitioning
Prototyping
Glue Logic
Abstractionss
SoC
Assembly
Block
Implementation
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig 2.24
Timing Closure
Die Area
Time-to-Market
Power and Signal
Integrity
Reliability
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig 2.25
100%
75%
9%
11%
14%
17%
15%
35%
9%
22%
7%
13%
27%
50%
27%
26%
>10
6-10
4-5
3
2
1
22%
28%
25%
13%
Number of
Place & Route
Iterations
28%
26%
12%
0%
4%
5%
7%
22%
<0.18 µ
0.25 µ
0.35 µ
0.50 µ
Drawn Feature Size
Source: Collett Intl. 1999 IC/ASIC Physical Design & Layout Verification Study.
Data based on 224 North American IC/ASIC product development teams.
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008
Fig 2.26
Digital Block
Digital Block
Noise Generation
• Increased Digital Logic
• Higher Speeds of Operation
• Sharp Slew rates
Analog
RF
PA
Digital Block
Noise Sensitivity
• Increased Signal
Resolution
• Higher Performance
• Lower Operating
Voltages
Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008