Transcript AT91SAM9RL64 - prochild.com

AT91SAM9R(L)64 Technical Overview
AT91 Technical Support & Training Group
Version 1.2 January 2008
High-Performance Smart ARM Microcontrollers Based on ARM926EJ-S
AT91SAM9 Peripheral Differences
LCD
ADC
Touch
Screen
CAN
AC97
X
-
-
-
-
X
-
X
-
-
-
X
X
X
-
X
X
-
X
X
-
X
USB*
Device
USB
Host
Ethernet
EBI
Camera
SAM9260
FS
X
X
X
SAM9261
FS
X
-
SAM9263
FS
X
X
SAM9RL64
HS
-
-
AT91
* FS: Full Speed, HS: High Speed
(x2)
X
2
Microcontroller
AT91SAM9RL64
AT91SAM9RL64
Package
JTAG
Boundary Scan
System Peripherals
BGA217
15*15mm
JTAG ICE
AIC
DBGU
12MHz
OSC
WDT
POR
PIT
ROM
ARM926EJ-S
SAM-BA Boot
SRAM
4kB
DCache
RSTC
POR
SHDWC
32kHz
OSC
RTT
4kB
ICache
DataFlash Boot
64kB
Nand Boot
2-Channel DMA
TCM
I/D
PDC
UPLL*
LCD Controller
PMC
PLL
EBI
USB Dev. High Speed
PIOA/B/C/D
User
Int.
DMA
SDCard Boot
MMU
FIFO
DMA
SMC
(8/16/32-bit)
NAND
(8/16-bit)
ECC
SDRAM
(16/32-bit)
Electricals
CF
PCK 200 MHz
MCK 100 MHz
FIFO
VDDCORE = 1.1V
PCK 243 MHz
MCK 121 MHz
RTC
6-layer AHB Matrix
VDDCORE = 1.2V
RC OSC
EBI I/O Lines
1.8V or 3.3V
4 x GPBREG
Backup Unit (1.2V)
Peripheral Bridge
APB
User
Peripherals
32-bit
PDC
PDC
PDC
MCI
AC97
ADC
X6
Touch
Screen
PWM
x4
I/O
x118
16-bit
Timer
x3
* UPLL  UTMI PLL: Universal Transceiver Macrocell Interface PLL
Peripheral DMA
Controller: 22 channels
SDRAM Clock
100 MHz
PDC
PDC
PDC
USART
PDC
PDC
USART
SPI
TWI
SSC
TWI
SSC
PDC
PDC
USART
USART
PDC
3
AT91SAM9RL64 BootROM Memory
 AT91SAM9RL64 features on-chip BootROM memory
 BootROM embeds 4 applications:
 SAM-BA Boot
- Provides In-System Programming Solutions through
serial or USB communication channels
 DataFlash-Boot: boot from a raw binary
 NandFlash-Boot: boot from a raw binary
 SDCard-Boot: boot from a FAT12/16/32 formatted SDCard
4
AT91SAM9RL64 Internal Memory Mapping
0x0000_0000
0x0000_0000
ROM
0x0010_0000
EBI NCS0
0x0010_0000
SRAM A - ITCM*
0x0020_0000
SRAM A - ITCM*
0x0020_0000
SRAM B - DTCM*
0x0030_0000
SRAM B - DTCM*
0x0030_0000
64kB SRAM C
0x0040_0000
64kB SRAM C
0x0040_0000
ROM
0x0050_0000
ROM
0x0050_0000
ROM mapped by default
* At reset, the whole memory is assigned to Internal SRAM
5
AT91SAM9RL64 Embedded ROM
Power Up
Yes
SD Card Boot
on
MCI
BMS = 1
No
EBI Chip Select 0
User Application
NandFlash-Boot
on
EBI Chip Select 3
DataFlash-Boot
on
SPI Chip Select 0
Optional
SAM-BA Boot
6
AT91SAM9RL64 Power Supply
 Nine types of power supply pins
 VDDCORE pin:
Powers the core, internal memories and logic of the device (1.2V)
 VDDIOM pin:
Powers the External Bus Interface I/O line (1.8V or 3.3V)
 VDDIOP pin:
Powers the Peripherals I/O lines (3.3V)
 VDDBU pin:
Powers the Slow Clock Oscillator and a part of the system controller
(1.2V)
 VDDPLLA pin:
Powers the PLL (3.3V)
 VDDPLLB pin:
Powers the UTMI PLL (480MHz) and the 12MHz Oscillator (1.2V)
 VDDUTMIC pin:
Powers the USB v2.0 UTMI+ High Speed Transceiver Core (1.2V)
 VDDUTMII pin:
Powers the USB v2.0 UTMI+ High Speed Transceiver Interface (3.3V)
 VDDANA pin:
Powers the ADC cell (3.3V)
7
AT91SAM9RL64 Internal Power Management
1.8V or 3.3V
Domain
VDDIOM
EBI I/O Lines
VDDANA
ADC
VDDPLLA
3.3V
Domain
PLL
VDDIOP
Peripherals I/O
VDDUTMII
UTMI
Core + Interface
VDDUTMIC
VDDPLLB
1.2V
Domain
UTMI PLL
12MHz OSC
VDDCORE
POR
VDDBU
POR
Core & Logic
32kHz OSC, RC
RTT, RTC
SHDWC
4xGPBREG
8
AT91SAM9RL64 Power Consumption
 Power Consumption for VDDCORE = VDDBU = 1.2V @ 25°C
9
AT91SAM9RL64 Peripherals Consumption
 Power Consumption for VDDCORE = VDDBU = 1.2V @ 25°C
10
Shared Bus Drawbacks
CPU
CORE
Bus Arbiter
ARM926EJ-S
SPI
Internal
SRAM C
Peripheral
DMA
Controller
(PDC)
SDRAM
EBI
LCD
Controller
LCD DMA
Controller
11
AT91SAM9 AHB MATRIX:
Multi-master systems with increased bus bandwidth
• The Matrix is a multi-layer
bus architecture that
connects several masters to
several slaves
MASTER 2
AHB
MATRIX
• Enables parallel access
paths between multiple
masters and slaves in a
system
SLAVE
SLAVE
SLAVE
MASTER 1
SLAVE
Layer Master 1
Layer Master 2
Layer Master n
12
AT91SAM9RL64 AHB MATRIX:
Multi-master systems with increased bus bandwidth
ARM926EJ-S
Instruction
Fetch code
Internal
SRAM C
Peripheral
DMA
Controller
(PDC)
SPI Read RHR
Peripheral
Bridge
LCD DMA
Controller
Frame Buffer
EBI
SPI
SDRAM
13
AT91SAM9RL64 AHB MATRIX Implementation
• 6 Layers Matrix
• 6 Masters
• 6 Slaves
• Master Remap command
• One Layer per Master
Masters
ID
Slaves
ID
DMA Controller
0
Internal ROM
0
USB HS Device DMA
1
Internal SRAM 64kB
1
LCD Controller DMA
2
LCD Controller User Interface
2
Peripheral DMA Controller
3
USB HS Device DPRAM (FIFO)
3
ARM926EJ-S Instruction
4
EBI
4
ARM926EJ-S Data
5
Peripheral Bridge
5
14
AT91SAM9RL64 AHB MATRIX Arbitration
• The Bus Matrix provides an arbitration function that
reduces latency when two or more masters try to access
the same slave at the same time
• Two arbitration types:
• Round-Robin
• Fixed Priority
• Selection is made through the field ARBT of the Slave
Configuration Registers MATRIX_SCFGx
15
AT91SAM9RL64 AHB MATRIX
Round Robin Arbitration
• If two or more master’s requests arise at the same time, the
master with the lowest ID number is first serviced then the others
are serviced in a round-robin manner.
• Three Round-Robin Algorithms
• No default master
• At the end of the current access, if no other request is pending, the slave is
disconnected from all masters. This configuration incurs one latency cycle for the
first access but saves power
• Last access master
• At the end of the current transfer, if no other master request is pending, the slave
remains connected to the last master that performs the access
• Fixed master
• At the end of the current access, the slave remains connected to its fixed default
master
16
AT91SAM9RL64 AHB MATRIX
Fixed Priority Arbitration
• For each slave, a fixed priority number for each master may be
defined by the user through the priority registers MATRIX_PRASx
• If two or more master’s requests are active at the same time,
the master with the highest priority number is serviced first.
• If two or more master’s requests with the same priority are
active at the same time, the master with the highest ID number
is serviced first.
17
AT91SAM9RL64 Internal SRAM Memory
 AT91SAM9RL64 embeds a 64Kbyte SRAM split in 4 blocks
of 16KBytes.
 At reset, the whole Internal SRAM memory is accessible
and mapped @ 0x300_000
 This Internal SRAM can be allocated to threes areas:
 Internal SRAM A: ARM926EJ-S Instruction TCM (0x100_000)
 Internal SRAM B: ARM926EJ-S Data TCM (0x200_000)
 Internal SRAM C: remaining SRAM (0x300_000)
18
AT91SAM9RL64 Tightly Coupled Memory (TCM)
 TCM sizes are configurable
 Modulo 16 Kbytes and up to 32 Kbytes
 Instruction/Data TCM can be mapped:
 @ 0x100_000/0x200_000 through AHB at bus speed (MCK)
 anywhere in the ARM926 instruction/data memory space (using
CP15 instructions) at processor speed (PCK)
 TCM Key Benefits
• Store real-time and performance critical code
• Deterministic and penalty free access
• Accesses are done at Processor speed (PCK)
19
AT91SAM9RL64 TCM Interests:
TCM are not used
ARM926EJ-S
Instruction
ARM926EJ-S
Data
Fetch code
32-bit @ MCK clock
Data access
32-bit @ MCK clock
Peripheral
DMA
Controller
(PDC)
SPI Read RHR
LCD DMA
Controller
Frame Buffer
Internal
SRAM C
Peripheral
Bridge
Peripheral
Bridge
SPI
EBI
SDRAM
20
AT91SAM9RL64 TCM Interests:
TCM are used
ARM926EJ-S
Instruction
ITCM Interface
Instruction
TCM
32-bit @ PCK clock
ARM926EJ-S
Data
DTCM Interface
Data
TCM
32-bit @ PCK clock
Peripheral
DMA
Controller
(PDC)
SPI Read RHR
LCD DMA
Controller
Frame Buffer
Peripheral
Bridge
SPI
EBI
SDRAM
21
AT91SAM9RL64 EBI Features
 External Bus Interface (EBI) frequency: up to 100Mhz
 Up to 6 Chip Select Lines
 16-bit, 32-bit SDRAM Memory support
 PC100 and Mobile SDRAM support through the embedded
SDRAM Controller:
- Deep Power Down Mode support
- Partial array self-refresh and others Mobile SDRAM features
 8-bit, 16-bit, 32-bit Static Memory
 NOR Flash
 RAM, PSRAM
 Memory mapped peripherals
 8-bit, 16-bit NAND Flash support through Static Memory
Controller (with Hardware ECC)
 Compact Flash support through Compact Flash glue-logic
22
AT91SAM9RL64 System Peripherals
 Reset Controller
 Based on 2 power-on reset cells (VDDCORE and VDDBU)
 Handles all the resets of the system without any external
components.
 Reports which reset occurred last.
 Drives independently or simultaneously the external reset, the
peripherals and processor resets.
 Advanced Interrupt Controller and Debug Unit
 Clock Generator & Power Management Controller (PMC)
 Watchdog Timer
 Prevents system lock-up (software deadlock)
 Generates general reset or processor reset only
 Periodic Interval Timer (PIT)
 Backup Unit (Shutdown Controller, RTT, RTC…)
23
AT91SAM9RL64 Backup Unit
 VDDBU POR
 16 bytes of back up data
 4 x 32-bit registers
 Real Time Timer
 Real Time Clock
 On Chip RC
 32KHz oscillator (with bypass)
 Slow Clock Selection Register
 Shutdown Controller
4 x Back Up Registers
(16 Bytes)
XIN32
XOUT32
SHDN
WKUP
VDDBU
32 kHz
OSC
RC
OSC
SHUTDOWN
Controller
POR
 Used to Control VDDIOx and VDDCORE.
RTT
 Software assertion of the SHDN Output pin.
 Programmable de-assertion from:
RTC
Reset Ctrl
- Wake-up WKUP pin
- RTT Alarm
- RTC Alarm
24
AT91SAM9RL64 Slow Clock Selection
 Slow Clock Configuration
Register (SCKCR)
 RCEN: enables on chip RC
 OSC32EN: enables 32K
oscillator
 OSCSEL: selects RC or 32K
oscillator
 OSC32BYP: 32K osc bypass
25
AT91SAM9RL64 User Peripherals
 4 Universal Synchronous/Asynchronous Receiver
Transmitters (USART)
 Hardware Handshaking support
 RS485 support
 ISO7816 support (T=0 and T=1)
 IrDA modulation/demodulation support
 Modem Signals Control
 Manchester Encoding/Decoding
 1 Master/Slave Serial Peripheral Interface (SPI)
 4 Fixed Chip select support
 Three-channel 16-bit Timer/Counters (TC)
 One 4-channel 16-bit PWM Controller (PWMC)
 2 Synchronous Serial Controllers (SSC)
26
AT91SAM9RL64 User Peripherals (cont.)
 Two I2C compatible Two-Wire Interface (TWI)
Master / Multi-master / Slave modes:
 TWI0: PDC in Master mode only
 TWI1: No PDC
 One Multimedia Card Interface (MCI)
 Compliant with Multimedia cards & SDCards & SDIO
 Touch Screen Analog-to-Digital Converter (TSADCC)
 6-channel ADC
- Support 4-wire resistive Touch Screen
- 2 general purpose channel ADC
 10-bit 220Ksamples/s
27
AT91SAM9RL64 User Peripherals (cont.)
 USB 2.0 High speed Device (480Mbits/sec)
 On-chip USB V2.0 UTMI+ High Speed transceiver (Universal
Transceiver Macrocell Interface)
 Integrated 4 kBytes FIFO and dedicated 6-channel DMA
 7 endpoints
 2-channel DMA controller
 Up to 64k Memory to Memory Transfers
 Single block transfers
 Multi-block transfers
- Contiguous blocks
- Block Chaining (Linked List)
- Destination and Source Address Auto-reload
28
AT91SAM9RL64 User Peripherals
 One AC97 Controller (AC97C)
 Compatible with AC97 Component Specification V2.2
 Can interface with a single analog front end
 Three independent RX Channels and three independent TX
Channels
 Time Slot Assigner that can assign up to 12 time slots to a channel
 Channels support mono or stereo up to 20-bit sample length
- Variable sampling rate AC97 Codec Interface (48 kHz and below)
29
AT91SAM9RL64 User Peripherals (cont.)
 AT91SAM9RL64 LCDC STN panel Features
 Single and dual scan, color and monochrome LCD panels
 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan interfaces
 Up to 16 gray levels for monochrome and up to 4096 colors for color
panel
 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for
monochrome
 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized)
for color STN display
 AT91SAM9RL64 LCDC TFT panel Features
 Single scan active TFT LCD panel
 Up to 24-bit single scan interfaces
 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (nonpalletized)
30
AT91SAM9RL64 User Peripherals (cont.)
 AT91SAM9RL64 LCDC Common Features
 Configurable screen size up to 2048 columns and 2048 lines
 DMA controller
- for reading the display data from an external memory.
- 2D Memory Addressing for virtual Frame Buffer management :
allows management of a frame buffer larger than the screen
size and moving the view over this virtual frame buffer.
31
AT91SAM9RL64 vs. AT91SAM9R64
AT91SAM9 Peripheral Differences
LCD
ADC
Touch
Screen
CAN
AC97
X
-
-
-
-
X
-
X
-
-
-
X
X
X
-
X
X
-
X
X
-
X
-
-
ADC
only
-
-
USB*
Device
USB
Host
Ethernet
EBI
Camera
SAM9260
FS
X
X
X
SAM9261
FS
X
-
SAM9263
FS
X
X
SAM9RL64
HS
-
-
AT91
SAM9R64
HS
-
* FS: Full Speed, HS: High Speed
-
(x2)
X
X
Only
16-bit
33
Microcontroller
AT91SAM9RL64
AT91SAM9RL64
Package
JTAG
Boundary Scan
System Peripherals
BGA217
15*15mm
JTAG ICE
AIC
DBGU
12MHz
OSC
WDT
POR
PIT
ROM
ARM926EJ-S
SAM-BA Boot
SRAM
4kB
DCache
RSTC
POR
SHDWC
32kHz
OSC
RTT
4kB
ICache
DataFlash Boot
64kB
Nand Boot
2-Channel DMA
TCM
I/D
PDC
UPLL*
LCD Controller
PMC
PLL
EBI
USB Dev. High Speed
PIOA/B/C/D
User
Int.
DMA
SDCard Boot
MMU
FIFO
DMA
SMC
(8/16/32-bit)
NAND
(8/16-bit)
ECC
SDRAM
(16/32-bit)
Electricals
CF
PCK 200 MHz
MCK 100 MHz
FIFO
VDDCORE = 1.1V
PCK 243 MHz
MCK 121 MHz
RTC
6-layer AHB Matrix
VDDCORE = 1.2V
RC OSC
EBI I/O Lines
1.8V or 3.3V
4 x GPBREG
Backup Unit (1.2V)
Peripheral Bridge
APB
User
Peripherals
32-bit
PDC
PDC
PDC
MCI
AC97
ADC
X6
Touch
Screen
PWM
x4
I/O
x118
16-bit
Timer
x3
* UPLL  UTMI PLL: Universal Transceiver Macrocell Interface PLL
Peripheral DMA
Controller: 22 channels
SDRAM Clock
100 MHz
PDC
PDC
PDC
USART
PDC
PDC
USART
SPI
TWI
SSC
TWI
SSC
PDC
PDC
USART
USART
PDC
34
Microcontroller
AT91SAM9R64
AT91SAM9R64
Package
JTAG
Boundary Scan
System Peripherals
JTAG ICE
AIC
TCM
I/D
PDC
UPLL*
DBGU
12MHz
OSC
WDT
POR
PIT
SAM-BA Boot
SRAM
4kB
DCache
RSTC
POR
SHDWC
32kHz
OSC
RTT
ROM
ARM926EJ-S
4kB
ICache
DataFlash Boot
64kB
Nand Boot
2-Channel DMA
PMC
PLL
EBI
USB Dev. High Speed
PIOA/B/C/D
BGA144
10*10mm
DMA
SDCard Boot
MMU
SMC
(8/16-bit)
NAND
(8/16-bit)
ECC
SDRAM
(16-bit)
Electricals
CF
PCK 200 MHz
MCK 100 MHz
FIFO
VDDCORE = 1.1V
PCK 243 MHz
MCK 121 MHz
RTC
5-layer AHB Matrix
VDDCORE = 1.2V
RC OSC
EBI I/O Lines
1.8V or 3.3V
4 x GPBREG
Backup Unit (1.2V)
Peripheral Bridge
APB
User
Peripherals
16-bit
PDC
PDC
ADC
X3
MCI
PWM
x3
I/O
x49
16-bit
Timer
x3
* UPLL  UTMI PLL: Universal Transceiver Macrocell Interface PLL
Peripheral DMA
Controller: 18 channels
SDRAM Clock
100 MHz
PDC
PDC
PDC
USART
PDC
PDC
USART
SPI
TWI
SSC
PDC
PDC
USART
USART
35
AT91SAM9R64 AHB MATRIX Implementation
• 5 Layers Matrix
• 5 Masters
• 5 Slaves
• Master Remap command
• One Layer per Master
Masters
ID
Slaves
ID
DMA Controller
0
Internal ROM
0
USB HS Device DMA
1
Internal SRAM 64kB
1
Reserved
2
Reserved
2
Peripheral DMA Controller
3
USB HS Device DPRAM (FIFO)
3
ARM926EJ-S Instruction
4
EBI
4
ARM926EJ-S Data
5
Peripheral Bridge
5
36
AT91SAM9R64 EBI Features
 External Bus Interface (EBI) frequency: up to 100Mhz
 Up to 4 Chip Select Lines
 16-bit SDRAM Memory support
 PC100 and Mobile SDRAM support through the embedded
SDRAM Controller:
- Deep Power Down Mode support
- Partial array self-refresh and others Mobile SDRAM features
 8-bit, 16-bit Static Memory
 8-bit, 16-bit NAND Flash support through Static Memory
Controller (with Hardware ECC)
 Compact Flash support through Compact Flash glue-logic
37
AT91SAM9R64 User Peripherals
 No AC97 Controller
 No LCD Controller
 1 Synchronous Serial Controller (SSC0)
 1 Master/Slave Serial Peripheral Interface (SPI)
 2 Fixed Chip select support
 One 3-channel 16-bit PWM Controller (PWMC)
 1 Two-Wire Interface (TWI0) Master / Multi-master / Slave
modes:
 PDC in Master mode only
 (Touch Screen) Analog-to-Digital Converter (TSADCC)
 No touch screen feature
 Only 3 general purpose channels ADC
 10-bit 220Ksamples/s
38
AT91SAM9R64 User Peripherals
 4 Universal Synchronous/Asynchronous Receiver
Transmitters (USART)
 No Modem Signals Control
 No external clock SCKx pins
 Hardware Handshaking support only for USART1
 RS485 support only for USART1
 No ISO7816 support (no SCKx pins)
 IrDA modulation/demodulation support
 Manchester Encoding/Decoding
 Three-channel 16-bit Timer/Counters (TC)
 Some TC Channel x I/O Lines missing
 One TC Channel External Clock Input missing
39
AT91SAM9RL64 vs AT91SAM9R64
40
AT91SAM9RL64 vs AT91SAM9R64 (cont.)
41
AT91SAM9RL64 vs AT91SAM9R64 (cont.)
42
AT91SAM9RL-EK Overview
AT91SAM9RL-EK Kit
 AT91SAM9RL-EK Evaluation Kit
 5V power supply
 Supported by SAM-ICE
 Fitted with an AT91SAM9RL64
 DVD-ROM
 IAR, GreenHills and Keil toolchains
 Getting started, Datasheets…
44
Board Diagram
USB
connector
IO (B)
RS-232/Debug
connector
IO (C)
SAM9RL
IO (A)
SDRAM
Expansion
Connector (EBI)
IO (D)
RS-232
connector
JTAG
connector
LCD
NAND
Flash
DataFlash
Prototyping
area
MMC/SD
Slot
Line
out
Line
in
Micro
input
Power
45
AT91SAM9R(L)64 Technical Overview
High-Performance Smart ARM Microcontrollers Based on ARM926EJ-S