Transcript Subject - Western Connecticut State University

Computer Views
Computer Architecture
CS 215
Some terms
 K (kilo)
 M (mega)
 G (giga)
 T (tera)
=
=
=
=
210 = 1,024
220 = 1,048,576
230 = 1,073,741,824
240 = ???
Viewpoints
 User
 Programmer
 Architect
 Logic Designer
User’s View
 Often called end-user
 Does not see implementation, only end
results
Programmer’s View
 Functional behavior of a computer as
viewed by a programmer



Instruction Set Architecture (ISA)
Functional units
Data type sizes, operations, etc.
Instruction Classes
 Data movement
 Arithmetic/Logic
 Control flow
More terms
 Machine state

Contents of all registers and machine memory
 Procedure calls

Used to implement functions
 Machine interrupts

Unexpected interruptions to normal execution
 Exceptions

Internal problems with normal execution
Architect’s View
 Structural relationships that are not
visible to the programmer


Driven by performance needs & csot
constraints
Interfaces, clock frequency, memory, etc.
Logic Designer’s View
 Works in both Boolean logic and
implementation
 Concerned with …


Design correctness
Constraints
 Ex. Fan-in and Fan-out
 Uses various design and analysis tools
Von Neumann Model
 Input Unit
Memory
Unit
Input Unit
Arithemtic
and Logical
Unit (ALU)
Control Unit

Output Unit
Provides
instructions
and data to
system
Von Neumann Model
 Output Unit
Memory
Unit
Input Unit
Arithemtic
and Logical
Unit (ALU)
Control Unit

Output Unit
Returns
data from
system
Von Neumann Model
 Memory
Memory
Unit
Input Unit
Arithemtic
and Logical
Unit (ALU)
Control Unit

Output Unit
Storage for
instructions
and data
Von Neumann Model
 ALU
Memory
Unit
Input Unit
Arithemtic
and Logical
Unit (ALU)
Control Unit

Output Unit
Processes
data
Von Neumann Model
 Control Unit
Memory
Unit
Input Unit
Arithemtic
and Logical
Unit (ALU)
Control
Unit

Output Unit
Directs
processing
Von Neumann Model
 CPU
Memory
Unit

CPU
Input Unit
Arithemtic
and Logical
Unit (ALU)
Control
Unit
Output Unit
ALU and
Control Unit
combined
System Bus Model
Memory
Input &
Output
(I/O)
System Bus
CPU (ALU,
Registers,
& Control)
Data Bus
Address Bus
Control Bus
 Streamlined version of von Nuemann model




Data Bus
Address Bus
Control Bus
Power Bus (optional)
System Bus Model
System Bus
CPU (ALU,
Registers,
& Control)
Memory
Input &
Output
(I/O)
Data Bus
Address Bus
Control Bus
 Data Bus


Carries the information being transmitted
Sometimes implemented as data-in and data-out
buses
System Bus Model
System Bus
CPU (ALU,
Registers,
& Control)
Memory
Input &
Output
(I/O)
Data Bus
Address Bus
Control Bus
 Address Bus


Identifies where the information is being sent
“Memory” address identifies read/write location
System Bus Model
System Bus
CPU (ALU,
Registers,
& Control)
Memory
Input &
Output
(I/O)
Data Bus
Address Bus
Control Bus
 Control Bus

Describes aspects of how the information is being
sent, & in what manner
Machine Levels
User or Application Program Level
High-Level Language Level
Assembly Language / Machine Code Level
Control Level
Functional Unit Level
Logic Gates
Transistors & Wires
 Each level represents
an abstraction of the
computer
 Levels are kept
relatively independent
from one another
 Can allow for upward
compatibility
User or Application Program Level
User or Application Program Level
High-Level Language Level
Assembly Language / Machine Code Level
Control Level
Functional Unit Level
Logic Gates
Transistors & Wires
 User interacts with
computer
High-Level Language Level
User or Application Program Level
High-Level Language Level
Assembly Language / Machine Code Level
Control Level
Functional Unit Level
Logic Gates
Transistors & Wires
 Compiler maps data
types and instructions
to actual computer
hardware
 Can be recompiled in
different environments
 Source code
compatibility
Assembly Language /
Machine Code Level
User or Application Program Level
High-Level Language Level
Assembly Language / Machine Code Level
Control Level
Functional Unit Level
Logic Gates
Transistors & Wires
 Language of the
computer
 Instruction sets
 Assembler
substitutes
instruction codes for
mnemonics
 Different hardware
can support same
instruction set
Control Level
User or Application Program Level
High-Level Language Level
Assembly Language / Machine Code Level
Control Level
Functional Unit Level
Logic Gates
Transistors & Wires
 Effects register
transfers
 Control signals
transfer data from
register to register
 Hardwired Vs.
Microprogram control


firmware
microcontroller
Functional Unit Level
User or Application Program Level
High-Level Language Level
Assembly Language / Machine Code Level
Control Level
Functional Unit Level
Logic Gates
Transistors & Wires
 Internal CPU registers
 ALU
 Computer’s main
memory
Logic Gates, Transistors & Wires
User or Application Program Level
High-Level Language Level
Assembly Language / Machine Code Level
Control Level
Functional Unit Level
Logic Gates
Transistors & Wires
 The hardware!
 (More on this later)
Question?
User or Application Program Level
High-Level Language Level
Assembly Language / Machine Code Level
Control Level
Functional Unit Level
Logic Gates
Transistors & Wires
 Which levels map
to which views?
Machine Levels
 Floating point emulation




Due to insufficient resources
Floating point instructions are trapped
Replaced with machine code to imitate
floating point instructions
Emulation Vs. Math coprocessor
Typical Computer System
 Input

Keyboard
 Output

Monitor
 Storage

Floppy disk, hard disk, CD-ROM, etc.
 Motherboard

CPU, RAM, expansion slots, bus, etc.