Transcript Lock vs. Lock-Free memory - Southern Illinois University

Lock vs. Lock-Free memory
Fahad Alduraibi, Aws Ahmad, and Eman Elrifaei
Outline
• CPU vs. Memory performance development
• Single-core vs. Multi-core CPU
• Synchronization
– Lock-based
– Transactional Memory (TM)
• Related Research
• Lock-based vs. STM performance
• Methodology
• Expected results
• References
CPU vs. Memory performance
107x
106x
Growth
105x
104x
103x
102x
10x
1x
1975 1980 1985 1990 1995 2000 2005
Intro. Multi-core
Dual Core CPU Chip
CPU Core
and
L1 Cache
CPU Core
and
L1 Cache
Bus Interface
and
L2 Cache
Main Memory
Multi-core CPU
• Advs.
– Higher clock rates for cash coherency
– Increased data processing
– Decreased latency
• Challenges
– OS Support
– Software Adjustment
– Synchronization (shared data)
Synchronization
• Synchronizing concurrent access to
shared memory by multiple threads
• Lock Based Synchronization
– Coarse-grained Locking
– Fine-grained Locking
• Lock Free Synchronization
– Transactional Memory
Lock-Based Synchronization
• if (lock == 0) lock = myPID;
/* lock free - set it */
Thread 1
Lock
Thread 2
• Drawbacks
– Deadlock
– Priority inversion
– Finer-grained locks  Complex & Overhead
Transactional Memory Synch.
• Lock-free controlling access to shared
memory in concurrent computing.
• Transactions are atomic:
temp = a;
e.g.
Swap (a,b);
a = b;
b = temp;
– Executes completely (commits) or has no effect
(aborts)
• A transaction runs in isolation (serialization)
TM Advantages
•
•
•
•
•
Easier parallel programming.
Good parallel performance.
Eliminates deadlocks.
Avoids priority inversion and convoying.
Fault tolerance (in case a thread dies).
TM Implementations
Hardware TM
Fast but
limited
Hybrid TM
Uses both
HTM & STM
Software TM
Slow but
flexible
Related research
• McRT-STM: A High Performance Software
Transactional Memory System for a Multi-core
Runtime
• Compared performance between STM different
Schemes
• Also compared performance between STM and
locks with a set of programs
• Built in C++
• Measurements done on 16-processor IBM x445
SMP system with Xeon MP 2.2 Ghz Running
Redhat EL3
Related research
• Hybrid-TM
– implementation of both software and hardware
transactional memory schemes.
Hybrid Transactional Memory.
Trans in
By: Sanjeev Kumar† Michael
Chu‡ Christopher J. Hughes†
Partha Kundu† Anthony Nguyen†
†Intel Labs, Santa Clara, CA
Trans out
HW
SW
‡University of Michigan, Ann Arbor
System resources
Lock-based vs. STM performance
• Recent Research Studies showed that STM can
perform as good as Fine-Grain Lock-Based
system
Source: “McRT-STM: A High Performance Software
Transactional Memory System for a Multi-Core Runtime”
Lock-based vs. STM performance
• The performance is application dependent too
Source: “McRT-STM: A High Performance Software
Transactional Memory System for a Multi-Core Runtime”
Our Methodology
• Comparing Performance of Lock-Based
Synchronization System with SXM Software
Transactional System
• Building a benchmark to run programs written with
locks
• The benchmark will be programmed in C#
Language
• The inputs (parameters) to the benchmark will be
(Program name, #threads)
• The output of the benchmark is execution time
Our Methodology (Cont.)
• To Measure Execution time
– Record Start Time
– Loop for number of Iterations
– Record End Time
– Subtract End Time – Start Time, divide by
number of Iterations
• Many Iterations are used to calculate the
performance accurately
• Different scenarios can be applied to calculate the
average
Execution Time
Expected Results
STM
Lock
prog1
prog2
prog3
prog4
References
• M. Herlihy and J. E. B. Moss. Transactional memory:
Architectural support for lock-free data structures. In Proc.
20th Annual International Symposium on Computer
Architecture, pages 289–300,May 1993.
• N. Shavit and D. Touitou. Software transactional memory.
Distributed Computing, Special Issue(10):99–116, 1997.
• S. Kumar, M. Chu, C. J. Hughes, P. Kundu, and A. Nguyen.
Hybrid transactional memory. In Proc. ACM SIGPLAN
Symposium on Principles and Practice of Parallel
Programming, Mar. 2006.
• McRT-STM: A High Performance Software Transactional
Memory System for a Multi-Core Runtime
• “How to Write High-Performance C# Code" By: Jeff
Varszegi, .NET Developer's Journal
• Wikipedia.org