Transcript Slide 1

Some Definitions for ADCs
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CONVERSION TIME - is the time required for a complete measurement by
an analog-to-digital converter. Since the Conversion Time does not include
acquisition time, multiplexer set up time, or other elements of a complete
conversion cycle, the conversion time may be less than the Throughput
Time.
Number of Channels – Number of channels the ADC has to have to
provide sequential sampling (via multiplexing) of several sensors.
Range - Highest and lowest voltages that the board ADC can accept as
inputs. The ADC found inside most data acquisition systems is generally
only capable of understanding voltages. Hence, you may need to use signal
conditioning to convert the information, obtained from your sensors and
transducers, - to voltage.
Resolution - Smallest interval into which the amplitude measurement range
is divided. For example,12 bits equals 2^12 (or 4096) discrete values that
can be returned to software as measurement results. This is defined by the
number of bits that the ADC can use to represent the analog signal. For
example, if Vref = 1.2V, the resolution of 12-bit ADC is 1.2/4096 = 0.293mV
= 293uV.
Sampling Rate - Rate at which data is sampled. The faster the signal
changes, the higher sampling rate must be used to characterize the signal
accurately. Boards that have faster A/D converters can capture higher
frequency signals.
Characteristics of TI ADC
ADS1250
ADS1251
Resolution(Bits)
20
24
Sample Rate (max)
25kSPS
20kSPS
# Input Channels
1
1
Architecture
Delta-Sigma
Delta-Sigma
Input Configuration Range
Vref/PGA (1-8)
Vref
Interface
Serial SPI Interface
Serial SPI
Interface
INL (+/-)(Max)(%)
0.00001
0.00000
INL(Max)(+/-LSB)
0.002
0.0015
DNL(Max)(+/-LSB)
1
1
ENOB(Bits)
18
19
Characteristics of TI ADC, Cont.
ADS1250
ADS1251
Power Consumption(Typ)(mW)
75
7.5
Reference Mode
Ext
Ext
Analog Voltage AV/DD(Min)(V)
4.75
4.75
Analog Voltage AV/DD(Max)(V)
5.25
5.25
Digital Supply(Min)(V)
4.75
4.75
Digital Supply(Max)(V)
5.25
5.25
Pin/Package
16SOIC
8SOIC
Operating Temperature Range(°C)
-40 to 85
-40 to 85
Rating
Catalog
Catalog
Approx. Price (US$)
8.70 | 1ku
6.00 | 1ku
SAMPLING THEORY
• Samples are snapshots of the changing values
(give me your examples)
• Sampling has to be done with frequency at least
two times more than the highest frequency
component in the original (periodic) signal –
Nyquist criteria (Harry Nyquist of Bell Telephone
Laboratories, 1924)
• If sampling is too slow, - reconstruction of the
original signal will be wrong. It is called “aliasing”
Aliasing
Digitizing Unipolar Analog Signal
Digitizing the wave 16 times
2.5
Digitized Values
2
1.5
Analog Value
1
Digitized Values
0.5
0
0
100
200
-0.5
Angle, Deg
300
400
3-bit Digitizer Sampling 128 times per Wave
Analog and Digitized Values
2.5
2
1.5
3-bit Digitizing
Analog Value
1
0.5
0
0
100
200
Angle, Deg.
300
400
Errors of ADC
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Quantization Error
Offset Error
Gain Error
Differential Linearity Error
Integral Linearity Error
Aperture Error
Total Unadjusted Error (TUE)
Transfer Function of a 3-bit ADC
Quantization Error
• Quantization error is caused by the finite resolution of
the ADC, and is an unavoidable imperfection in all types
of ADC. The magnitude of the quantization error at the
sampling instant is between zero and half of one LSB.
• The transfer function of an ideal N-bit ADC is shown in
Figure 2.37 (*). The quantization error for any ac signal
which spans more than a few LSBs can be approximated
by an uncorrelated sawtooth waveform having a peak-topeak amplitude of q, the weight of an LSB.
* See the book’s section 2.3.
Quantization Noise
Quantization Error for ADC is
Output - Input
Differential and Integral Nonlinearity Errors
of ADC
• Differential Nonlinearity (DNL): An ideal A/D converter
exhibits code transitions at analog input values spaced
exactly 1LSB apart (1LSB = VFS / 2^n). DNL is the
deviation in code width from the ideal 1LSB code width.
A DNL error less than –1LSB can cause missing codes.
• DNL is a critical specification for image-processing,
closed-loop, and video applications. This is a dc
specification, where measurements are taken with neardc analog input voltages.
• Integral Nonlinearity Error is the integral of DLE over
the full range.
Differential Nonlinearity Error
Offset Error
• Offset Error: Offset error is the difference in voltage
between the ideal first code transition and the actual
code transition of an A/D converter. This is a dc
specification, where measurements are taken with neardc analog input voltages.
• In a unipolar device, offset error is the difference
between the first measured transition point (lowest in
voltage) and the first ideal, transition point. (See Figure
19.) Unipolar Offset Error is measured and calculated as
shown in the following equation:
Offset Error = (V[0:1]-(0.5)VILSB), where:
VILSB – Ideal LSB Voltage,
V[0:1] – Analog Voltage of first transition
Unipolar Offset Error
Offset Error – difference
between actual first code
transition point and ideal first
code transition point.
Offset Error can be
calibrated in hardware or
FW/SW.
Gain Error
• From mathematical expression of the ADC
transfer function: D = C + G*A, where:
D – digital code, C – offset, G – gain, and A –
analog value.
• May be defined as the gain error contribution (in
mV or LSB) to the total error at full-scale.
• Gain can be calibrated out at near full-scale by
different measures: changing the transfer
function of the sensor or conditioning circuitry, or
by changing the voltage reference of the ADC.
Aperture Error (from Wikipedia)
• Imagine that we are digitizing a sine wave x(t) =
Asin(2πf0t). Provided that the actual sampling
time uncertainty due to the clock jitter is Δt, the
error caused by this phenomenon can be
estimated as Eap <= |X‘(t)∆t| <= 2Aπf0∆t.
• The error is zero for DC, small at low
frequencies, but significant when high
frequencies have high amplitudes. This effect
can be ignored if it is drowned out by the
quantizing error. Jitter requirements can be
calculated using the following formula:
,
where q is a number of ADC bits.
Aperture Error Example
Clock Edge Delay Causes Error
2.5
Digitized Values
2
1.5
Analog Value
1
Digitized Values
0.5
0
0
50
100
150
200
-0.5
Time
250
300
350
400
Total Unadjusted Error
Successive Approximation Register
(SAR) ADC
How the SAR ADC Works
• The SAR starts by forcing the MSB (Most Significant bit)
high (for example in an 8 bit ADC it becomes 1000 0000
– Why?), the DAC converts it to VAREF/2. The analog
comparator compares the input voltage with VAREF/2. If
the input voltage is greater than the voltage
corresponding to the MSB, the bit is left set, otherwise it
is reset.
• After this comparison is done, the next significant bit is
set (=VAREF/4) and a comparison is done again with the
input voltage. The procedure is followed till all the bit
positions are compared.
• At the end of all the bit comparisons we get the
corresponding digital output for the analog input.
• The clock frequency must be equal to the sampling
frequency multiplied by the number of bits of resolution
desired.
Single Slope ADC
How Single Slope ADC Works
• Upper Amplifier without feedback works as a
comparator.
• Bottom Amplifier has a capacitor in the feedback
and works as an integrator
• MOSFET is needed to reset the integrator
• Counter is reset on falling edge (not the level) of
the (counter’s) CLR signal
• Output buffer is latched on the front edge of the
(buffer’s) CLK signal
• Counter counts clock signals until CLR goes
high
ExpressPCB Installation
• Nothing tricky (click OK several times):
• www.expresspcb.com
ExpressPCB Installation, Cont.
• Happy End:
Concept of SCH Design
• Designing the schematic using schematic
symbols (from standard library or from
yours)
– Selecting symbols and placing them on your
schematic sheet
– Arranging symbols in logical order and
connecting them with “wires”
– Editing schematic and annotating components
– Check schematic for netlist errors command
from the File menu
Concept of PCB Design
• Designing PCB layout using footprints of
components from standard library (or
yours)
– Selecting footprints from the library and
placing them on layout drawing
– Arranging footprints in logical order and
aligning them using grid (adjustable)
– Linking schematic to PCB from the
ExpressPCB program's File menu
Selecting a Component
Schematic Example
Selecting a Footprint
Layout for the Above