Transcript Digital Video Engineering (1)

Low-Power H.264 Video Compression
Architecture for Mobile
Communication
Student: Tai-Jung Huang
Advisor: Jar-Ferr Yang
Teacher: Jenn-Jier Lien
Outline
 Introduction
 Low-Resolution ME
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 Effect of Pixel Truncation for VBSME
 Two-Step Algorithm
 Hardware Implementation
 Simulation and Implementation Results
--Performance of the Proposed Two-Step Algorithm
--Performance of the Proposed Architectures
--Energy Saving on H.264 System
 Conclusion
 Reference
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Introduction(1/4)
 In this paper, we analyze the effect of truncating pixels for
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smaller block partitions and propose a method of improve the
frame prediction.
 Our proposed method is able to reduce the total computation
and memory access compared to conventional full-search
method without significantly degrading picture equality.
 The proposed architectures are able to save energy compared
to the conventional full-search architecture.
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Introduction(2/4)
 Video compression allows video data to be compressed
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before it is sent through a wireless channel ,however video
compressed is computation-intensive and dissipates a
significant amount of power.
 The sum of absolute difference (SAD), as follows
M 1 N 1
SAD(i, j )   C (k , l )  R(i  k , j  l )
k 0 l 0
C (k , l ) : the current MB
R(i  k , j  l ) : the candidate MB
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Introduction(3/4)
 Pixel truncation can be used to reduce the computational load.
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 MPEG-4 AVC/H.264 allows variable block size for motion
estimation (VBSME) and a better prediction at smaller block
partitions is achieved for objects with complex motion.
 Due to the truncation error, there is a tendency for smaller
blocks to yield matched candidates, which could lead to the
wrong motion vector. Thus, truncating pixels using smaller
blocks results in poor prediction.
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Introduction(4/4)
 According to relative papers, we could propose a low-power
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algorithm and architecture for ME using pixel truncation for
smaller block sizes.
 The search method reduces the computational cost and
memory access without significantly degrading the prediction
accuracy.
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Low-Resolution ME(1/2)
 To improve the frame prediction, we proposes a two bits
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transform (2BT) where the original image is converted into
two bits using the threshold value derived from the local
image standard deviation.
 More than 0.2 dB improvement is achieved with this lowresolution method as compared to one bit transform (1BT).
 The pixel’s least significant bits (LSBs) are adaptively
truncated depending on the quantization parameter (QP).
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Low-Resolution ME(2/2)
 Truncating the pixel’s most significant bits (MSBs) was
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discussed in relative paper.
 In low-resolution ME, most methods focus on reducing the
power by minimizing the computational load.
 While direct pixel truncation has the potential to reduce
memory access, it is often at the expense of a decrease in
PSNR in some motion types.
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Effect of Pixel Truncation for VBSME(1/3)
 Since the LSBs of a data word experience a higher switching
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activity, significant power reduction can be achieved by
truncating these bits.
 Further reduction can be achieve if the number of truncated
bits (NTBs) is increased.
 This makes pixel truncation attractive to minimize power in
ME.
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Effect of Pixel Truncation for VBSME(2/3)
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 This shows that for 16×16 block size, the truncated pixel is more likely to
have the same matched candidate as in the untruncated pixel.
 This shows that there are more matched candidates using truncated pixel
for 4×4 block size, which could lead to incorrect motion vectors.
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Effect of Pixel Truncation for VBSME(3/3)
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 From Table II, for full pixel resolution (NTB = 0), the prediction accuracy
improves as the block size decreases.
 The PSNR drop for predictions using smaller block sizes is higher.
 This shows that pixel truncation is not suitable for smaller block sizes.
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Two-Step Algorithm(1/6)
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Two-Step Algorithm(2/6)
 In this paper, we propose a method of pixel truncation for
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VBSME, as follows:
step 1): Truncating pixels for larger block sizes can result in
better motion prediction compared to small block
sizes.
step 2): At higher pixel resolutions, smaller block sizes can
result in better predication compared to the larger
block sizes.
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Two-Step Algorithm(3/6)
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 Fig. 2 shows the simulation results using truncated pixels with several
matching criteria.
 From the figure, at high NTB, error-based matching criteria gives a poor
result compared to the boolean-based matching criteria.
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Two-Step Algorithm(4/6)
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 To ensure that the overall computation cost does not exceed the
conventional full search computation, the second search is done at a
quarter of the size of the first search area.
 Increasing the refinement area will not only increase the total
computation, but also increase the memory access, as shown in Table III.
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Two-Step Algorithm(5/6)
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Two-Step Algorithm(6/6)
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 The second search center is defined as
 m vxmin  m vxmax m vymin  m vymax 
,


2
2


with search range, p2  (1/ 2) p1
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Hardware Implementation(1/6)
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Hardware Implementation(2/6)
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Hardware Implementation(3/6)
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Hardware Implementation(4/6)
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Hardware Implementation(5/6)
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Hardware Implementation(6/6)
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Performance of the proposed Two-Step Algorithm(1/4)
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Performance of the proposed Two-Step Algorithm(2/4)
 Tables VI and VII show the PSNR difference using the
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



proposed method against the conventional full-search ME
(FS).
Different frame sequences that represent various types of
motion from low to high are used in this experiment: Akiyo,
Mobile, Foreman, and Stefan.
From above table, our method is able to achieve a good
prediction with a smaller PSNR drop compared to the other
method.
This is due to the prediction error and search range limitation
during the first and second searches, respectively.
The PSNR drop varies depending on the level of detail of the
frame. For a frame with less object detail, the PSNR drop is
slightly higher.
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Performance of the proposed Two-Step Algorithm(3/4)
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 Table VIII shows the average PSNR drop for several existing ME
techniques.
 As shown in Table VIII, our method shows superior performance
compared to other techniques for 16×16 to 4×4 block sizes.
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Performance of the proposed Two-Step Algorithm(4/4)
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 From the graphs, it can be seen that the proposed method could achieve
good performance, close to the conventional method, without
significantly degrading the picture quality.
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Performance of the Proposed Architectures(1/5)
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Performance of the Proposed Architectures(2/5)
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Performance of the Proposed Architectures(3/5)
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Performance of the Proposed Architectures(4/5)
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Performance of the Proposed Architectures(5/5)
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Energy Saving on H.264 System(1/2)
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Energy Saving on H.264 System(2/2)
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Conclusion
 This paper has presented a method to reduce the
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computational cost and memory access for VBSME using
pixel truncation.
 In this paper, we have proposed a two-step search to improve
the frame prediction using pixel truncation.
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Reference
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[1] Advanced Video Coding for Generic Audiovisual Services, ITU-T
Recommendation H.264 & ISO/IEC 14496-10 (MPEG-4) AVC, 2005.
[2] C.-Y. Chen, S.-Y. Chien, Y.-W. Huang, T.-C. Chen, T.-C. Wang, and L.-G. Chen,
“Analysis and architecture design of variable block-size motion estimationfor
H.264/AVC,” IEEE Trans. Circuits Syst. I: Regular Papers, vol. 53, no. 3, pp.
578–593, Mar. 2006.
[3] Z.-L. He, C.-Y. Tsui, K.-K. Chan, and M. L. Liou, “Low-power VLSI design for
motion estimation using adaptive pixel truncation,” IEEE Trans. Circuits Syst.
Video Technol., vol. 10, no. 5, pp. 669–678, Aug. 2000.
[4] A. Bahari, T. Arslan, and A. T. Erdogan, “Low computation and memory access
for variable block size motion estimation using pixel truncation,”in Proc. IEEE
Workshop Signal Process. Syst. 2007 (SiPS ’07), pp. 681–685.
[5] A. Bahari, T. Arslan, and A. Erdogan, “Low-power hardware
architecture for vbsme using pixel truncation,” in Proc. 21st Int. Conf.
VLSI Design, Hyderabad, Andhra Pradesh, 2008, pp. 389–394.
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