Transcript Design Flow

FPGA Design Flow
Verilog RTL Coding
Verilog test
bench
Verilog
model
Functional/Gate
simulation
& Verification
Verilog
Netlist
Design Stage Tools
Verilog Design
Text Editor
Emacs, Nedit, Vi
Verification
Modelsim SE
Leda
Synthesis
Xilinx ISE - XST
Synplify Pro
Pyhsical Design &
Implementation
Xilinx ISE
Xilinx Impact
sdc
Logic Synthesis
ngc
ucf
Physical Layout
par
Device Configuration
bit
Digital Design Flow
Verilog test
bench
Verilog
RTL
Verilog Coding
Functional/Gate
Simulation/Verification
Logic Synthesis
Verilog
Netlist
Test-Insertion
_pre.sdf
_post.sdf
test.scr
Static Timing Analysis
Floorplanning/
Place & Route
ctgen.con
scr
Clock Tree Insertion
Final Layout
techfile.lef
techfile.gcf
*.lef
*.tlf
*.def
Timing Extraction
Final Design Check
DRC/LVS
gds2
Design Stage Tools
Verilog Design
Text Editor
Emacs, Nedit, Vi
Verification
Mentor - Modelsim SE
Synopsys - Leda
Synthesis
Synposys - Design Compiler
Test Insertion
Synopsys - TetraMax
Mentor - Fastscan
Static Timing Anal.
Synopsys - Primetime
Place & Route
Cadence - Sensemble/
SOC Encounter
Synopsys - Apolllo
Clock Tree Insertion
Cadence - CTgen
Timing Extraction
Synopsys - StarRXT
Cadence - Pearl
DRC/ANT Checking
Cadence - Assura, Dracula
Mentor – Callibre
LVS
Cadence - Assura, Dracula
Mentor – Callibre
Analogue Design Flow
Schematic Entry
Simulation
Layout
techfile.lef
techfile.gcf
*.lef
*.tlf
*.def
Physical Verification /
Extraction
Post-Layout Simulation
gds2
Design Stage
Tools
Schematic Entry
Composer
Simulation
Spectre
Layout
Virtuosso
Pyhsical Verification/
Extraction
Assura
Calibre
Post-Layout Simulation
Spectre
Mixed Signal Design Flow
Cadence - SpectreVerilog
Cadence -UltraSim
Digital Flow
Analog Flow
Co-simulation
Environement
Verilog test
bench
Verilog
RTL
Verilog Coding
Schematic Entry
Behavioural
Modelling
Functional/Gate
Simulation/Verification
Logic Synthesis
Verilog
Netlist
Test-Insertion
scr
Simulation
test.scr
Layout
_pre.sdf
Static Timing Analysis
Floorplanning/
Place & Route
ctgen.con
_pst.sdf
Clock Tree Insertion
Final Layout
techfile.lef
techfile.gcf
*.lef
*.tlf
*.def
Timing Extraction
Final Design Check
DRC/LVS
Physical Verification /
Extraction
Post-Layout Simulation
gds2
techfile.lef
techfile.gcf
*.lef
*.tlf
*.def
gds2