Transcript Circuit Simulation of RF Systems

Virtual Algorithm Design for RF Receivers
Sanjay A. Khan
k.inc
k.inc proprietary, all rights reserved
1
Wireless Digital Communication
Upconversion
Downconversion
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Noise removal at receiver provides opportunities for more aggressive utilization of bandwidth
•
Sources of “noise”:
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mixing in of adjacent carriers due to circuit non-linearities
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thermal and shot noise in receiver
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phase noise introduced by frequency synthesizer in receiver
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substrate noise from digital circuitry in receiver
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Only thermal and shot noise in receiver are truly stochastic with no autocorrelation
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All other sources of noise are “deterministic” and can be theoretically removed at the receiver
•
Shot and thermal noise are the only truly “unremovable” impairments. Orders of magnitude
improvements in efficiency that could be made possible with infinite digital processing power at
receiver
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2
Wireless Communication Landscape
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3
Next Generation Wireless Communications Standards
Next Generation Wireless LANs: IEEE 802.11n
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Raw throughput between 135Mb/s and 540Mb/s
Pre-standard products emerging now (2006 standards)
Wireless Personal Area Network:
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Wireless USB (WUSB): 802.15.3a
Up to 480Mb/s throughput with a range of 10 meters
Look for WUSB to appear in laptop chipsets in 2006
Broadband Wireless Access / Metropolitan Area Networks:
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IEEE 802.16 WiMAX
Throughput up to 70Mb/s with a range up to 20 miles
Licensed spectrum (2.5-2.6 GHz) or Unlicensed (2.4 & 5.8 GHz)
802.16a products emerging now
802.16e provides support for mobility and handoffs (2006)
IEEE 802.20 MobileFi
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Throughput up to 12Mb/s with a range < 10 miles
Supports mobile users up to 250 Km/h in licensed spectrum bands
Some pre-standard technologies being fielded (e.g., Flarion.Nextel)
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4
Effect of Impairments on QAM Modulated Signals
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Q
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I
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QAM 16 Constellation
RF signal transmitted:
I cos(RF t   )  Q sin(RF t   )
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Shannon’s Channel Capacity Formula
C  2 B log 2 (1 
S
)
N
For a given baud rate (channel bandwidth), higher SNR allows
more aggressive constellations, and consequently higher bits per
second
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5
Opportunities to Algorithmically Improve Spectral Efficiency
Infinitely powerful
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Baseband DSP
Need for high fidelity RF
circuit simulator
that can capture all RF
impairments at circuit
Level accuracy
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while co-simulating with
Baseband simulator
• Compression due to non-linear gain can be statically compensated
• Adjacent channel mixing impairments can be equalized out if receiver is powerful enough to detect
symbols from all adjacent channels and then construct an equalizer
• Symbol rotation due to PLL is autocorrelated, so is theoretically cancelable
• Substrate Noise effects can be detected and nulled out with clever design
• Beam steering technologies allow higher SNR
• Uncorrelated noise introduced by the LNA and downconversion mixer is unremovable. This is the floor
noise level is determined by temperature and the Boltzmann constant and cannot be equalized out.
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6
Product Optimization Via Virtual ProtoTyping
Many, many opportunities for clever, optimal design of RF transceivers – perhaps
two decades of innovation to come
Product roll-out for future generations must follow an evolution trajectory that is
consistent with what consumers will incrementally pay for incremental performance
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7
Value Proposition
•
Current wireless technologies use the precious resource of bandwidth in an abysmally inefficient way
(WCDMA/UMTS, WiFi, FlashOFDM)
RFIC Vendors need to differentiate themselves by trying to achieve:
• The least amount of compression, rotation and symbol spread in the received constellation (for higher bit
rates)
• at the lowest cost and power
Wireless
Food
Chain
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Worldwide Wireless Service Provider Market
Worldwide RF Communication Equipment Market
Worldwide RF Communication IC Market
Worldwide RF Transceiver IC Market
CAD for Xcvr Alg. Exploration (BB Alg. Sim, Ckt Extraction, RF Ckt Sim)
Accurate RFIC Circuit Simulation (key enabler for virtual proto-typing)
$1 Trillion
$300 Billion
$50 Billion
$20 Billion
$1 Billion
$100 Million
Real proto-typing is extremely expensive ($millions per pilot run), turn around is painfully slow (many
weeks), and it does not provide algorithm designers an opportunity to “play” with quick feedback
$100 million opportunity to provide wireless xcvr algorithm designers with a cheap(er) virtual sandbox that
they trust. Incorrect algorithm optimization due to poor simulation fidelity is a big pain for system architects
PAIN KILLER: A fast, highly accurate virtual proto-typing tool that can efficiently handle all components of
an RFIC (Power Amp, Upconverter, LNA, Downconverter, VCO, Phase Detector, Frequency Dividers, Filters),
with all impairments (ckt element noise sources, gain compression, adjacent channel mixing, PLL phase
noise, substrate noise) simulated at circuit level accuracy
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8
Sources of RF Signal Impairments
PA
Low Noise Amplifier
• High gain, high sensitivity
• Non-linearities cause blockers to mix into
channel of interest => spread in rcvd
constellation
• Non-linear gain causes compression of
rcvd constellation
• Component Noise Power (Thermal /
Shot) is comparable to power of rvcd
signal - causes spread in rcvd
constellation
Air Interface
LNA
(attenuation + blockers)
Power Amplifier
• Non-linear (class E)
• Non-linearities cause symbol
spread due to mixing in of
adjacent channels (APCR)
• Non-linear gain causes
compression of rcvd
constellation
RF
UpConv
BB (I/Q)
Downconversion Mixer
• LO Phase noise causes
angular spread in rcvd
constellation
• Component noise causes
spread in rcvd constellation
(cyclostationary)
DnConv
Rcvd Constellation
Automatic Gain Control
• Non-linearities causes symbol
spread due to mixing in of
adjacent channels
• Gain Compression causes
compression of rcvd
consellation
LO
LO
PLL
• VCO phase noise causes
rotation of rcvd constellation
• PLL dynamics cause angular
spread in rcvd constellation
AGC
Loop Filter
Counter
VCO
Frequency Synthesizer
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9
Competitive Landscape
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No vendor offers a circuit simulation tool that does end-to-end symbol in / symbol out
simulation of the entire RF system at the circuit level, accounting for all sources of noise.
For standalone transmitter (Power Amplifier), several vendors offer time domain symbol in /
symbol out simulators using Envelope Transient Harmonic Balance. Agilent, Xpedion and
AWR offer the most widely used solutions. K.inc’s solution will be faster than any of the
above.
Berkeley Design Automation offers circuit level tools to simulate phase noise in standalone
VCOs and standalone open loop PLLs. No vendor offers a circuit level tool that simulates the
entire frequency synthesizer. Agilent’s Envelope Transient algorithm is inappropriate for PLL
circuits.
No vendor offers a time domain solution for the low noise amplifier and downconversion
mixer which accounts for phase noise in the LO (freq. synthesizer) and component noise in
the LNA and mixer. Berkeley Design Automation’s technical team have
No efficient circuit level simulation tool is available for the AGC.
In lieu of the non-availability of circuit level time domain simulation tools, many vendors
offer tools to create time domain behavioral models of the above circuit components after
pre-characterizing them with frequency domain circuit simulation (Cadence JK Models,
Agilent and AWR with AM/AM and AM/PM models). Xpedion offers a Neural Network based
tool to create behavioral models.
All the above behavioral models have highly questionable and suffer from mathematically
unbounded inaccuracy.
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10
k.inc Technologies for Robust RFIC Circuit Simulation
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Device models (like BSIM4) re-derived using Automatic Differentiation for robustness
Table models with speed / accuracy trade-offs appropriate for different portions of the
system. Third order derivative accuracy for RF mixers and amplifiers, first order accuracy (at
considerably higher speed) for “large signal” circuits. To be patented.
Homotopy algorithms (based on LOCA) for robust DC convergence and Autonomous Periodic
Steady State computation.
Multi-rate Partial Differentail Equation (MPDE) Circuit Solver with Shur Complement matrix
algorithms and Volterra Series techniques to allow lightning fast simulation of RF
transmitters. To be patented.
LTI (Linear Time Invariant) simulation techniques with Volterra Series corrections for high
speed simulation of LNAs and downconversion mixers. Novel algorithm to rigorously handle
phase noise introduced by LO; Ornsten-Uhlenbeck algorithm for time domain noise
simulation. To be patented.
Fokker Plank solver for characterizing phase noise in VCOs. Fast Timing circuit simulation
algorithms for handling other blocks of PLL. To be patented.
Adaptive Volterra Series algorithm for simulating AGCs. To be patented.
All numerical computation tuned to exploit hyper threading and other features of modern
processors; custom for device models, based on widely used open source packages for
matrix computations.
System simulation set up to exploit multi-threading and multiple workstations on a LAN
Extensive use of robust software packages (PVM, MPI, PETSC, UMFPACK, ADOL-C, LOCA,
QT).
k.inc proprietary, all rights reserved
11
Product Positioning
c
S
ircuit
imulator
for
h
a
n
n
igh frequency
nalog
R
oise-limited
non-linear circuits
and
o
ptimization sandbox
for
n
on-linearities and noise
k.inc proprietary, all rights reserved
12
Bottom Up Market Analysis
•
Wireless Standards needing circuit-level symbol in / symbol out simulation capability:
- WiFi/WWiSE (802.11x), WCDMA/UMTS, 4G, Flash OFDM, WiMax, 802.16x, Bluetooth,
UWB
• Potential customers engaged in design of RFICs for above standards:
- Agere, Airgo, Airoha, Analog Devices, Atheros, Bermai, Broadcom, Cambridge Silicon
Radio, Conexant, Envara, Freescale, GCT, IceFyre, Infineon, Intel, Intersil, Marvell,
Mobilian, Parthus, Philips, PlexTek, Qualcomm, Railink, RFMD, Signia Tech, Silicon Wave,
ST Micro, Synad, Systemonic, TI, Wireless Interface Tech, Wiscom, Zeevo, Zyray, …
•
RFIC Market projected to grow to $37 Billion by 2006, with 663 projected design starts per
+
year over all the above standards .
•
Each design start will need one team license for cShannon.
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cShannon will be licensed for $100,000 per design team per design start
•
Addressable market is approx. $70 Million per year!
+
k.inc proprietary, all rights reserved
Cahners InStat, 2003
13
Exit Strategy
NYSE CDN
•
•
•
•
•
• $1.13B revenue
Xpedion - not yet public
• Significant player in analog and mixed
signal
NSDQ
SNPS
Investors:
verification
markets
(Virtuoso)
• $1.18B revenue
- Menlo Ventures
Berkeley
Design
Automation
•
Declining
presence
in RFIC extraction
• Significant
player in and
analog and mixed signal
Applied Wave Research
- Telesoft Partners
•
Investors:
simulation
hence
technology
partnership
with
simulation
markets
•
Investors:
- Telos Venture Partners
- Bessemer
Venture
Partners
Agilent
• Ckt. Sim. Technology via acquisitions
- CMEA
Venture
Partners
- Redwood
Venture
Partners
- Woodside
• Homegrown Ckt. Sim.
Technology:(Hspice)
- MetaSoftware
- Synopsys
? Fund
Spectre
- Anagram
First Round:
$12M
First
Round:
$13M
Spectre
RF
(outdated
- Epictechnology)
First Round:
Second
Round:
? $5M
• Ckt. Sim. Technology
via acquisitions
• Extraction
technology from Avanti acquisition
•
No
revenue
yet
BLDA
(ADS)
• No presence in RFIC verification market
? revenue
?• revenue
•
Very
little
information
available
on
what
circuit
Celestry
(Ultrasim)
• Significant investor in AWR
•
Envelope
Transient
HB
+
frequency
domain
RFIC freq. domain circuit
level
simulation +
NSDQ
MENT
NYSE A
NSDQ
LAVA
simulation
and
analysis
technolgies
are
offered.
•
Significant
investor
in Xpedion
VolterraTransient
Series simulation
(Microwave
Office)
Envelope
HB for Power
Amps (Golden
• •$692M
revenue
•
Test
equipment
vendor
$127M
revenue
CTO
is Amit
Mehrotra
whoindustry
has done
prior work
• Extraction
technology
from
partner,
Gate)
• •Minor
player
in line
analog
and
mixed signal
• Presence
in RF- not
EDA publicly
due to Eesof
acquisition
Emerging
full
EDA
vendor
Aplac
traded
in US
in
Fokker
Planck
based
simulation
of
phase
NSDQ ANST
NoOEA
extraction technology
simulation
markets
•
Market
leader
in
frequency
domain
RF
circuit
• noise
No presence
in simulation
market
(digital
• Pure
RFIC
player
in
oscillators.
Other
TAB
members
• Behavioral
Simulation
engine
(Visual
System/
• $57M
revenue
Behavioral
Simulation
using
Neural
Network
• Weak
RFIC
ckt
simulation
technology
(ELDO)
simulation
(ADS) simulation (Fast RF IC
analog / RF)
• RFIC
circuit
(Jaideep
Roychowdhury,
U. third
of Minn.)
Simulator)
• RFIC
freq.level
domain circuit level simulation
Models
(Model
Compiler)
- uses
partyhave
• •Strong
player
in
extraction
(Calibre)
• Strong
in RFIC extraction (IC-CAP)
No significant
presence in extraction
market
Module)
worked
in
macro-modeling
of
RF
components.
(Nexxim)
behavioral
simulator player in RFIC verification
• •Not
significant
• Cadence
partner for
RFIC design; strong
Mayaextraction
look
to filltechnology
out product
line in these areas
• RFIC
extraction
(Electromagnetic
Module)
No
offered.
• RFIC
extraction
(Q3D) + electromagnetic
integration
with
Cadence(System
RFIC design
flow
• Behavioral
Simulation
Module)
solver (HFSS)
• Behavioral Simulation (Ansoft Designer)
RFIC Simulation + Analysis Vendors
Full Line RFIC EDA Vendors (Extr. + Sim.)
Full Line EDA Suppliers
Technology Supplier
k.inc proprietary, all rights reserved
14
Development Status and Test Plan
•
All coding completed
- Matrix computations
- MPDE, LTI, Fokker-Planck, Ornstein-Uhlenbeck, Homotopy for PSS & DC Conv., Fast Timing
- Automatically differentiation of non-linear device models, table models, Volterra Series stamps
- distributed computation and message passing
•
•
125,000 lines of new C++ code (not including any packages).
Testing milestones:
- Validation of automatically differentiated models
- Validation of first and third order table models
- Time domain transient simulation
- DC convergence with LOCA homotopy
- LOCA homotopy for autonomous periodic steady state
- Volterra correction stamps
- MPDE with Volterra series and Shur Complement
- Fast timing transient algorithm
- LTI algorithm for LNA + downconversion mixer
- Ohrnstein-Uhlenbeck noise simulation algorithm
- Fokker Plank based oscillator phase noise algorithm
- PVM set-up for multi threading and distributed computing
k.inc proprietary, all rights reserved
15
Angel Funding Needs
•
•
•
•
6 man-months to complete coding
12 man-months to prove in one end-to-end design from friendly customer
Total initial seed - $250,000
Expectations for final valuation
– 33% of a $70 million market
– Net profitability at steady state with 50% margin: $10 million per year
– “Market Cap” at steady state: $100 million, assuming PE of 10
– Angel offered 10% equity in company, for 40X return on investment if exit on full
maturity
– Angel’s ROI reduced for early exit via acquisition, but still 10X even if eventual buyer
gets 4X discount to offset higher risk of early acquisition
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16