Transcript Gain calibration of pipelined ADCs

FE8113 ”High Speed
Data Converters”
Part 2: Digital background
calibration
Gain errors and calibration
- Introduction to gain error calibration and test
signal injection in pipelined ADCs
Pipelined ADC
Vin  (Vin  1 )   2  2  1
Stage 1
backend
Vin
2
ε1
-
εbe
2
 be  2  1
Y
Y  Vin  1   2   be  2  1   2 Vin   be
Digital error correction
1 bit, no error correction:
1.5 bits, error correction:
offset
offset
out
out
ref
ref
ref
2
ref
2
ref
2
ref
Stage output:
0
ref
2
0
ref
ref
2
ref
in
ref
4
ref
4
ref
2
ref
2
ref
ref
0
1
1
ref
2
ref
Stage output:
00
00
01
01
10
10
Backend MSB:
0
1
1
0
1
Backend MSB:
0
1
0
1
0
1
Sum:
00
01
01
10
11
Sum:
00
01
01
10
10
11
Offset translates directly to distortion at
the output
Offset within +/-Vref/4 corrected by
redundant bits
in
MDAC gain error
φ1:
QCr  QCf  Vin  VCM    Cr  C f 
QCr  QCf  Vin  VCM    Cr  C f 
Cf
+
Vin
Cr
+
-
VCM
-
+
Vout
A
-
-
+
Cr
Cf
φ2:
Cf
 d V
 d V
ref 
 vx   Cr  Vout   vx   C f  Vin  VCM   Cr  C f 
ref   vx    Cr  Vout   vx    C f  Vin   VCM    Cr  C f 
+
d  Vref
Cr
vx 
-
+
Vout
A
vx 
-
+
-
+
Cr
Cf
-
MDAC gain error
Cf
φ2:
+
d  Vref
Vout 
Vout


 d Vref 
  Cr   Vout 
A 
A



  C f  Vin   Cr  C f 

Cr
vx 
-
+
Vout
A
vx 
-
+
-
-
+
Cr
Cf
Vout


 1 
A
  2  Vin  d  Vref   

2

V

d

V



in
ref
2
A 2
1 
A

Vout
d

 2  Vin  Vref
2

d
 A

 2  Vin  Vref

2
 A 2


  Ge

out
ref
ref
2
 ref
 ref
2
 ref
4
ref
4
 ref
2
 ref
ref
2
ref
in
Pipeline with gain error
Vout_1_ideal
Vin_be
Vin
Stage 1
2
Y
Ge1
backend
Pipeline with gain error
Vout_1_ideal
Vin_be
Stage 1
backend
Vin
2
ε1
-
Ge1
εbe
2
Y
Y  2 Vin  be   2  1  1 Ge1 
Calibration of gain error
Vout_1_ideal
Vin_be
Stage 1
backend
Vin
2
ε1
-
Ge1
εbe
2
l1
Y
Y  2 Vin  be  l1   2  1  1 Ge1  l1 
l1 
1
 Y   2 Vin   be  l1 
Ge1
Calibration of multiple stages
Calibrated backend
Vin
Stage 1
Stage 2
Ge1
22
backend
Ge2
2
l1
l2
Y
1
1
l1 
, l2 
 Y   2 Vin   be  l1  l2 
Ge1
Ge2
Calibration, alternative
implementation
Vin
Stage 1
Stage 2
1
1
Ge1
Stage 2
backend
1
Ge1  Ge2
Y
(Digital scaling factors between the stages are not shown here)
N
1
 Ge
i 1
i
Test signal injection
Vout_1_ideal
ts
Vin_be
Vin
Stage 1
Ge1
backend
1/4
2
l1
Y
Stage transfer function (TF)
out
ref
ref
2
 ref
 ref
2
 ref
4
ref
4
 ref
2
 ref
ref
2
ref
in
Stage TF with Vref/4 test signal
out
ref
ref
2
ref
ref
2
ref
4
ref
4
ref
2
ref
ref
2
ref
in
Stage TF, modified test signal, tsmod
out
ref
ref
2
 ref
 ref
2
 ref
4
ref
4
 ref
2
 ref
ref
2
ref
in
MDAC, holding phase, test signal
injection
Cf
ts
+
d Vref
Cts
Cr
vx
ts
-
+
Vout
A
vx
-
+
-
+
-
Cr
Cts
Cf
Vout
d


 2   Vin  Vref  tsmod   Ge
2


Test signal at ADC output
ts
Stage 1
mod
Vin
1/4
2
ε1
-
backend
Ge1
εbe
s1
1/4
be
2
s1+be
l1
Y
1
Y   2 Vin   be  l1   2  1  1  Ge1  l1    tsmod  1  Ge1  l1 
4
Measuring error energy
Vout_1_ideal
ts
Vin_be
Vin
Stage 1
Ge1
backend
1/4
2
l1
Correlator
Y
C
Correlate over a blocklength (BL) of millions of samples
1


C     2 Vin   be  l1   2  1  1  Ge1  l1    tsmod  1  Ge1  l1    ts
4

BL 
1
Error energy at the output, use this to
C    ts  tsmod 1  Ge1  l1  
adjust digital coefficient
4 BL
List of Papers

Test signal injection


Skip (& fill)



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
J.Ming, S.Lewis: “An 8-bit 80-Msample/s Pipelined Analog-to-Digital Converter With Background Calibration”
S.Sonkusale, J.Van der Spiegel: “Mixed-Signal Calibration of Pipelined Analog-Digital Converters”
Comparator Dithering




S.R.Sonkusale et.al: “Background Digital Error Correction Technique for Pipelined Analog-Digital
Converters”
X.Wang et.al: ”A 12-bit 20-Msample/s Pipelined Analog-to-Digital Converter With Nested Digital Background
Calibration”
J.P.Keane et.al: “Digital Background Calibration for Memory Effects in Pipelined Analog-to-Digital
Converters”
Reference voltage scaling



U-K.Moon, B-S.Song: “Background Digital Calibration Techniques for Pipelined ADC’s”
E.B.Blecker et.al: “Digital Background Calibration of an Algorithmic Analog-to-Digital Converter Using a
Simplified Queue”
Slow-but accurate parallel ADC


E.Siragusa, I.Galton: “A Digitally Enhanced 1.8-V 15-bit 40-MSample/s CMOS Pipelined ADC”
A.Gines et.al: “Full Calibration Digital Techniques for Pipeline ADCs”
J.Keane et.al: “Background Interstage Gain Calibration Technique for Pipelined ADCs”
J.Li et.al: “Background Calibration Techniques for Multistage Pipelined ADCs With Digital Redundancy”
Others
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

A.Abdelatty, K.Nagaraj: “Background Calibration of Operational Amplifier Gain Error in Pipelined A/D
Converters”
K.El-Sanakry, M.Sawan: “A New Digital Background Calibration Technique for Pipelined ADC”
B.Murmann, B.E.Boser: ”A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification”
Y.Chiu et.al: “Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital
Converters”