Transcript Behavioral Modeling of ADC using Verilog-A

High Frequency Behavioral Modeling of
Second-Order ΣΔ Modulators
By
George Suárez Martínez
Submitted in partial fulfillment of the requirements
for the degree of
MASTERS OF SCIENCE
in
Electrical Engineering
February 28, 2006
Presentation Outline




Motivation
Objectives
Second-order Multi-bit ΣΔ Modulator (ΣΔΜ)
Non-idealities





Jitter Noise
Thermal Noise
Capacitance mismatch
Individual Level Averaging (ILA)
Switched-capacitor (SC) integrator
 Results
 Conclusions
1
Motivation
 ΣΔ modulators (ΣΔMs) form part of the core of
many today’s mixed-signal designs as cornerstone
components of oversampled ΣΔ data converters
 ΣΔ converters have become a promising candidate
for high-speed, high-resolution, and low-power
mixed-signal interfaces
 Transistor-level simulation is the most accurate
approach (e.g. SPICE)
 Impractical for complex systems, long simulation
time… can take more than a day for a single case!
2
Motivation
 Alternate modeling techniques,




Finite-difference equations (z-transform)
Macromodels
Look-up tables
Behavioral models
 Accurate models are needed for low-power, high
speed applications (e.g. GSM and WCDMA)
 VHDL for Analog and Mixed Signal (VHDL-AMS)
becomes practical due to the mixed-signal nature of
ΣΔ Modulators
3
Objectives
 Develop an accurate behavioral model of a highspeed second-order multi-bit ΣΔΜ
 Make use and explore VHDL-AMS as the
modeling language
 Develop modular and reusable models for other
topologies of ΣΔΜs
 Validate the model with SPICE simulations
 Validate the model with experimental data for
target bandwidths of GSM (200kHz) and WCDMA
(2.0 MHz)
4
Second-Order ΣΔΜ (Ideal Model)
First Integrator
0.5
+
+
+
Second Integrator
1
+
-
+
+
-
5-level quantizer
0.5
1
DECODER + DAC
0.5
 Lack of non-idealities





Capacitance mismatch
Jitter Noise
Thermal Noise
Integrator Dynamics
Dynamic element matching behavior
5
Second-Order ΣΔΜ (Non-ideal Model)
Switched-Capacitor integrator dynamics
Slew rate limitations
Finite DC gain and bandwidth
Parasitic capacitances
Defective settling
Thermal noise
Jitter noise
g11
g12
DAC
g21
∫
g22
DAC
∫
5-level 3-bits
Flash ADC
4-bits
ILA
Mismatch in units
3-bits
4-bits
Decoder
4-bits
ILA algorithm
6
Noise Sources - Jitter Noise
 Non-uniform sampling.
δ
Δv
 For a sine wave the error can be approximated by,
 Assumed to be white, Gaussian noise
20
0
-20
Magnitude (dB)
-40
-60
-80
-100
-120
-140
0
0.5
1
1.5
Frequency (Hz)
2
2.5
5
x 10
7
Noise Sources - Thermal Noise
 Caused by the random motion of electrons due to
thermal energy
 For switched-capacitor ΣΔΜs thermal noise is due
the integrator:
1. switches resistance
2. operational transconductance amplifier (OTA)
 Based on track and hold operation of switchedcapacitor (SC) systems
8
Noise Sources - Thermal Noise
Sampling
Integration
9
Capacitance Mismatch
 Integrator gains are built using capacitor ratios
First Integrator
0.5
+
+
Second Integrator
1
+
+
quantizer
0.5
1
DAC
0.5
 In multibit architectures DAC mismatch introduces
harmonic distortion
 Dynamic Element Matching (DEM) such as
Individual Level Averaging (ILA) is employed
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Individual Level Averaging (ILA)
 Internal DAC unitary model
din
2
DAC
vout
unit1
Thermometer
decoder
+
unit2
 ILA algorithm transfer curves
ideal
vout
unit1
vout
unit2
vout
1.0
1.0
1.0
0.5
0.5
0.5
0
0
0
“00” “01” “10”
din
“00” “01” “10” din
Example
ideal
vout
0.5
0.25
0.25
0
0
din
“00” “01” “10” din
unit1
vout
0.5
“00” “01” “00” “01”
Error due
mismatch
unit2
“00” “01” “00” “01”
ILA on
din
11
Integrator Dynamics
vi
Φ1 Ci
Φ2
vr
Φ1
Φ2






Φ1
Cr
Cint
Φ2
Φ2
va
Cp
Φ1
Φ2
OTA
+
vo
CL Φ2
Φ1
Limited DC gain
Limited bandwidth
Slew rate limitations
Parasitic capacitances
gm, go relationship
Capacitive Loads
va
vo
+Io
+
va -
Φ1 Cinxt
gm(va+-va-)
go
Co
-Io
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Integrator transient behavior
 Possible scenarios in SC integrator transient
response:
 Linear va # Io/gm
 Partial Slew va > Io/gm and to $ t
 Slew va > Io/gm and to < t
 SR and to determine
the scenario
va
va-
vo
+Io
+
gm(va+-va-)
-Io
go
Co
OTA input voltage va
Slew
Linear
va = Io/gm
SR
to
t
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Linear
SC integrator transient equations
vai ,i  Io /g m
Slew
vai ,i  I o /g m
Partial
Slew
& t  to
vaf ,i
vaf ,i
vai ,i  I o /g m
& t  to
  g eq  vint ,eq
vint ,eq 

 exp
  vai ,i 
t
 C

A 
A

 eq 

vint ,eq I o sgn vai ,i    g eq  vint ,eq I o sgn vai ,i 
 vai ,i 

t

 exp

1 γ
g o,eq   Ceq  1  γ
g o,eq

vaf ,i
  g eq
 vint ,eq

I o vint ,eq 
t  to  
  sgn vai ,i  
 exp
gm
A 
A
 Ceq


gm Ci  Cr  C p
A  1

go
Cint
 Cp
vo  vo,n-1  1 
 Cint
go,eq
 Ci  Cr  C p 
 g m  g o 1 

Cint



 Ci
  C p  Ci  Cr
Cr
(-vi ) 
(-vr )   1 
 va ,n-1  
Cint
Cint

 Cint
 

 vaf ,i

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Simulation Results - Model vs SPICE
1. gm=1.16 mA/V and T=27oC.
Bandwidth
SPICE SNDR
Model SNDR
Error (%)
135kHz
86.56 dB
85.43 dB
1.31
270kHz
74.65 dB
70.35 dB
5.76
615kHz
54.99 dB
51.42 dB
6.50
2. gm=1.75 mA/V and T=27oC.
Bandwidth
SPICE SNDR
New Model SNDR
Error (%)
135kHz
86.10 dB
84.63 dB
1.71
270kHz
72.45 dB
70.30 dB
2.96
615kHz
53.62 dB
51.34 dB
4.25
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Simulation Results - Model vs SPICE
3. gm=1.9 mA/V and T=-30oC.
Bandwidth
SPICE SNDR
New Model SNDR
Error (%)
135kHz
89.90 dB
84.07 dB
6.48
270kHz
71.08 dB
71.04 dB
0.06
615kHz
53.53 dB
51.93 dB
2.99
4. gm=1. 9 mA/V and T=27oC.
Bandwidth
SPICE SNDR
New Model SNDR
Error (%)
135kHz
87.57 dB
84.98 dB
2.95
270kHz
72.73 dB
70.54 dB
3.01
615kHz
53.37 dB
51.89 dB
2.78
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Simulation Results for GSM
VHDL-AMS 76.57 dB
Actual data 74.50 dB
2.78% error
17
Simulation Results for WCDMA
VHDL-AMS 76.57 dB
Actual data 74.50 dB
2.41% error
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Results-Capacitance Mismatch
DAC mismatch
0.0%
0.1%
1.0%
SNDR (dB)
73.15
57.80
38.00
Individual Level Averaging off
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Results-Capacitance Mismatch
DAC mismatch
0.0%
0.1%
1.0%
SNDR (dB)
73.15
70.40
51.19
Individual Level Averaging on
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Results-Thermal Noise
Temperature
-30oC
27oC
100oC
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Results-Thermal Noise
Capacitor sizes
1X
2X
4X
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Results-Jitter Noise
Jitter models
Sampling deviation
70.7128 dB
Derivative
70.4322 dB
0.4 % relative
difference
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Results-Jitter Noise
Jitter standard
deviations
0.0 ns
0.1ns
1.0 ns
Input of 62 kHz
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Results-Jitter Noise
Jitter standard
deviations
0.0 ns
0.1ns
1.0 ns
Input of 120 kHz
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Comparison with Previous Models
Low power case
 Smaller Io
 Smaller DC gain
 Inclusion of go
Traditional Model
Presented Model
Admittance Matrix
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Speed*
Cycles
Admittance Matrix Model
VHDL-AMS Transient Model
8192
31 min 42 sec
15 sec
16384
1 hr 4 min 42 sec
30 sec
32768
2 hr 12 min 8 sec
1 min
65536
4 hr 13 min 5 sec
2 min 11 sec
A robust algorithmic-level time
complexity analysis is difficult!
*Simulations were carried on a Pentium 4 PC with 2GB memory running at 3.0GHz.
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Conclusions
 An accurate model of a second-order multi-bit
ΣΔΜ was developed
 Addresses several non-idealities such as:
 Jitter Noise
 Thermal Noise
 Capacitance Mismatch
 Integrator dynamics
 The integrator model an improved behavioral
characterization of the degrading effects of
settling errors on high-speed ΣΔΜs
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Conclusions
 Results against SPICE simulations show errors
less than 7%
 Results for GSM (200kHz) show 2.78% of error
 Results for WCDMA (2.0 MHz) show 2.41% of
error in comparison with ≥ 15% for the previous
model
 Behavioral modeling and simulation with VHDLAMS is a viable solution to the extensive
transistor-level simulation of ΣΔΜs
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References
1. J. C. Candy and G. C. Temes. “Oversampling Delta-Sigma Data Converters: Theory,
2.
3.
4.
5.
6.
7.
8.
9.
Design, and Simulation”. IEEE Press, 1992.
Norsworthy, S. R. and Schreirer, R. and Temes, G. C. “Delta-Sigma Data Converters:
Theory Design and Simulation”. IEEE Press, 1997.
G. Gomez and B. Haroun. “A 1.5 V 2.4/2.9 mW 79/50 dB DR SD modulator for GSMWCDMA in a 0.13 µm digital process”. ISSCC, pages 467–469, 2002.
Medeiro, F. and Perez-Verdu, A. and Rodriguez-Vazquez, A. “Top-Down Design of HighPerformance Sigma-Delta Modulators”. Kluwer Academic Publishers, 1999.
Sansen, W. Transient Analysis of Charge Transfer in SC Filters: Gain and Error Distortion.
IEEE Journal of Solid State Circuits, 22:268–276, 1987.
F.O. Fernandez and M. Jimenez. “Behavioral Modeling of Dynamic Capacitive Loads on
Sigma-Delta Modulators”. Seminario Anual de Automatica Electronica Industrial e
Instrumentacion, 1:119–122, 2002.
G. Suarez and M. Jimenez. “Behavioral Modeling of Sigma Delta Modulators using
VHDL-AMS”. IEEE Midwest Symposium on Circuits and Systems, 2005.
G. Suarez, M. Jimenez and F. Fernandez. “Behavioral Modeling Methods for SwitchedCapacitor ΣΔ Modulators”. Submitted to IEEE Transactions on Circuits and Systems
Journal.
G. Suarez and M. Jimenez. “Considerations for Accurate Behavioral Modeling of HighSpeed SC ΣΔ Modulators”. Submitted to IEEE International Symposium on Circuits and
Systems.
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Acknowledgements
•
•
•
•
•
Dr. Manuel Jiménez
Dr. Rogelio Palomera
Dr. Domingo Rodríguez
Felix O. Fernández
This work was partially supported by Texas
Instruments through the TI-UPRM Program.
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Questions?
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