Optimization of Delta-Sigma ADC for Column-Level Data Conversion in CMOS Image Sensors

Alireza Mahmoodi and Dileepan Joseph University of Alberta, Canada Email: [email protected], [email protected]

1

Outline

  Problem Solution (optimized delta-sigma ADC)  ADC structure in image sensors  Design and optimization of ADC  ADC simulation and performance evaluation  Conclusion

2

Problem

CMOS technology scales down Lower supply voltage More nonlinear analog circuits Smaller dynamic range Lower the achievable SNR

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Solution (delta-sigma ADC)

     Unlike Nyquist rate ADCs, oversampled ADCs (delta-sigma ADC) can filter the temporal noise in array sensors, achieving higher SNR.

Delta-sigma ADC is very tolerant to nonidealities of CMOS circuits.

Flexibility of trading the number of bits-per-pixel, with the frame rate in delta-sigma ADC is another advantage.

A few works have designed the DS-ADC for column or pixel level but with large power and area usage. Main issue of DS-ADC is power consumption and area usage which should be minimized (subject of this work).

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ADC structure in image sensors

 

Chip level ADC (One ADC for all of the pixels)

 High spatial resolution  But, high noise, high power, fast ADC is needed,

Pixel level ADC (One ADC for each pixel or group of pixels)

 Low noise, low speed ADC is needed, low power  But, low spatial resolution, high FPN.



Column level ADC (One ADC for each column or group of columns)

 A compromise between pixel level and chip level.

In this work a first-order column-level delta-sigma ADC will be designed.

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 Main concern was minimization of power and area .

Higher oversampling ratio is needed

Why first order?

Using first order structure Less sensitive to gain error of the integrator due to the capacitor mismatch More KT/C noise will be filtered Smaller capacitors could be used Small area because of simple structure Comparing to higher order structures, low power and smaller area could be achieved

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vin vmax

A

Modulator of first order structure

vmin

B

 1

d

Ci  1

d

vmin vmax  2

d D C

Cs  2 Cs  1 vcmi  2  1 vcmi + OTA + Ci + +  2

d

 2

d

 1

d

 The analog parts must be carefully designed because their nonidealities may limit the overall ADC performance.

B D C A

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Specifications of the modulator

  Mismatch is not the limiting factor. So, the minimum value for the capacitors in the integrator is determined by KTC noise.

P noise

 1

C

Power

_

Consumptio n



C

  The minimum value for Capacitors were determined.

Then, other parameters were designed.

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Operational Transconductance Amplifier

vdd vdd CMFB (input)   OTA is the most critical Component Folded-cascode OTA structure with gain boosting was used.

vin1 vb2 vin2 out1 + OP-n + + OP-p + out2 vb1 vb2 vb1 gnd

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DDA-CMFB circuit.



OTA needs a common-mode feedback (CMFB) circuit .

(1) Switched capacitor CMFB CMFB (output)  It has large swing and linearity.

out1  Loads the output of the OTA, reducing its UGB and SLR.Large area is needed (2) We used a differential-difference amplifier CMFB (DDA-CMFB).

 It can offer enough swing and linearity with very small area.

vcm vdd gnd out2 Ib

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Decimator design

Coefficients generator Coefficients Chip level Modulator output Reset Accumulator Register 3 Reset ADC output bits Decimator at column level   The coefficients of the decimation filter are generated at the chip level.

The decimation filter is only an accumulator at the column level which consumes 60μW power.

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Simulation results

SNR versus OSR 100 90  Simulation was done for a 0.18μm CMOS process using Cadence and Simulink.

80 70 60 50 (a) (b) (c) (d) 40  SNR versus OSR based on: 30 (a) Theoretical calculation 20 10 1 (b) Simulink using 5000 samples (c) Simulink using 50 samples 10 2 Oversampling Ratio (OSR) (d) Cadence (modulator) and Simulink (decimator) using 50 samples

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10 3

Performance evaluation

 Figure-of-merit (FM) is defined as This work

FM

 2

b P f N

State of the art ADC Best case 0.4pJ

Worst case 1.3pJ

1.51pJ

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Conclusion

   The design of a first-order delta-sigma ADC for column level data conversion in an image sensor has been presented.

Since the first-order modulator is not sensitive to gain error due to capacitor mismatch, minimum-size capacitors may be used to minimize the power consumption and area usage.

A new structure for decimator was introduced.

   The proposed ADC has a low power consumption of 210 μW .

Simulation results are very close to the theoretical values Presently, the design is being laid out in a 0.18μm process. Ultimately, the design will be fabricated and tested.

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10 

m

Thank you Questions?

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Acknowledgements

 This work was sponsored by the Natural Sciences and Engineering Research Council of Canada and the Mary Louise Imrie Award.

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References

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Survey of DS-ADC in CMOS Image sensors

TYPE Column Number of bits Frame rate Power 12 40 115mW Frame Size 100*1k Column Column (this work) 10 12 30 50 50mW 210mW 100*100 1k*1k

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