Transcript Document

Filter design
from Σ-Δ ADC to incremental Σ-Δ ADC
Donglijun 2013-4-28
TJU ASIC center
index
filter design of Σ-Δ ADC
filter design of incremental Σ-Δ ADC
difference between the two filters
filter design of Σ-Δ ADC
• Σ-Δ ADCs are widely used in telecommunication
and multimedia applications.
• The key property of Σ-Δ ADC
• ①to achieve high resolution do not rely on
precisely matched analog elements
• ②rely on oversampling, noise-shaping and
digital post-filtering.
• ③can be integrated well into today’s fine linewidth CMOS technologies.
filter design of Σ-Δ ADC
• Modulators of Σ-Δ ADC push the noise from low frequency rate to
high frequency rate. So to achieve high resolution, the key point of
Σ-Δ ADC is its digit filter’s suppression of high frequency.
• The function of the filter are as follow:
• ①filtering
• ②decimating
• ③coding
• There is some parameters
•
for Σ-Δ ADC filter:
• ①decimating rate(D)
• ②bandwidth
• ③SNR
A normal architecture for Σ-Δ ADC
filter
Modulator fs
output
1bit
CIC filter
fs/32
FIR
fs/64
Half-band
filter
fs/128
Digital
output
16bits
Filter architecture
CIC filter
FIR filter(half band filter)
Fir example
bandpass
example
H(1)
1.94
H(1)
1.5
H(2)
-0.19
H(2)
0
H(3)
-0.25
H(3)
-0.25
H(4)
0
H(4)
0
H(5)
-0.25
H(5)
-0.25
H(6)
-0.19
H(6)
0
H(7)
1.94
H(7)
1.5
Introduction to incremental Σ-Δ ADC
• Unfortunately, these classical ΣΔ structures
are not well suited for instrumentation and
measurement (DC) applications.
• Require:
• ①very high absolute accuracy and linearity
• ②high dynamic range and signal-to-noise
ratio
• ③Hertz wide bandwidth(nearly DC input)
2
Reset
u
z 1
1  z 1
积分器
V1
Reset
z 1
1  z 1
积分器
Reset
V2
di
比较器
Reset
1
1  z 1
1
1  z 1
滤波器
滤波器
dout
Filter design for IDC
3 Typical structure of decimation filter
 CoI filter
 Sinc filter(CIC)
 Optimal filter
Canceling periodic noise
Line frequency noise
 S/H and the error of S/H
 Periodic noise suppression digit filter
Typical structure for IDC filter
Sinc filter(CIC)
Cascade Integrate Comb
CoI filter
Cascade Of Integrated
Weighting factor and cycle number
Specifications and appropriate
architectural solutions
Specification
Architecture
Low power and area consumption
Second or third order 1-bit modulator
with COI digital filter
Possible lowest delay
COI digital filter
Lowest number of cycles
Optimized filter with new algorithm
Suppression of periodic noise
Digital sinc-filter
Wide-range suppression of line
frequency
Optimized sinc-filter
Suppression both 50-60Hz
simultaneously
Optimized sinc-filter
Uniform output quantization error
Modulator & same-order COI filter
sinc filter → rotated sinc filter
rotated sinc filter
rotated sinc filter
• From left to right D=32,64,128 bottom D=128
Design deference between
Σ-Δ filter and incremental Σ-Δ filter
Σ-Δ filter
incremental Σ-Δ filter
architecture
3-Integreted-filter
1 filter
delay
High
Low
Number of cycles
High
Low(key design point)
Suppression of high
frequency
Yes(key design point) No
Uniform output
quantization error
No
Yes
Power and area
consumption
High
low
application
Continuous
application
Discrete application
Work frequency
100Hz-1MHz
DC-100Hz
No filters can live without modulators
Thanks for the modulator designers
Reference
•
[1]Aziz, P.M.; Sorensen, H.V.; vn der Spiegel, J., "An overview of sigma-delta converters," Signal Processing Magazine, IEEE , vol.13,
no.1, pp.61,84, Jan 1996
•
[2]M Gustavsson, N Tan ."High performance switched-capacitor filter for oversampling Sigma-Delta digital to analog converters" US
Patent 6,614,374, 2003
•
[3]CH Dick, FJ Harris "Narrow-band filter including sigma-delta modulator implemented in a programmable logic device"US Patent
6,600,788, 2003
•
[4]H Murakami, T Kawai"Inertial force sensor including a sense element, a drive circuit, a sigma-delta modulator and a signal processing
circuit"US Patent 7,891,245, 2011
•
[5]de la Rosa, J.M., "Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey," Circuits and Systems I:
Regular Papers, IEEE Transactions on , vol.58, no.1, pp.1,21, Jan. 2011
•
[6]Gadde, Venkata Veera Satya Sair.,"Filter Design Considerations for High Performance Continuous-Time Low-Pass Sigma-Delta ADC."
2012.3.12 Texas A&M University academic thesis
•
[7]JL Gorecki, T Liu.,"Phase noise shaping using sigma delta modulation in a timing recovery unit"US Patent 7,720,160, 2010
•
[8]Lo Presti, L., "Efficient modified-sinc filters for sigma-delta A/D converters," Circuits and Systems II: Analog and Digital Signal
Processing, IEEE Transactions on , vol.47, no.11, pp.1204,1213, Nov 2000
•
[9]Agah A, Vleugels K, Griffin P B, et al. A High-Resolution Low-Power Incremental 61 ADC With Extended Range for Biosensor Arrays[J].
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45(6): 1099.
•
[10]Guo G, Wu D, Shen Y, et al. An optimal filter with optional resolution used in incremental ADC for sensor application[C]//Consumer
Electronics, Communications and Networks (CECNet), 2011 International Conference on. IEEE, 2011: 1042-1045.
Reference
•
[11]Kook S, Gomes A, Jin L, et al. Optimal Linearity Testing of Sigma-Delta Based Incremental ADCs Using Restricted Code
Measurements[C]//Mixed-Signals, Sensors and Systems Test Workshop (IMS3TW), 2011 IEEE 17th International. IEEE, 2011: 72-77.
•
[12]Maréchal S, Krummenacher F, Kayal M. Optimal filtering of incremental first-order sigma-delta modulators with sweep
input[C]//Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on. IEEE, 2010: 539-542.
•
[13]Maréchal S, Krummenacher F, Kayal M. Optimal filtering of an incremental second-order MASH11 sigma-delta
modulator[C]//Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on. IEEE, 2011: 240-243.
•
[14]Srinivas T, Madhuri V, Kumar D V J R, et al. Capacitor rotation method for removing gain error in sigma-delta analog-to-digital
converters: U.S. Patent 7,825,838[P]. 2010-11-2.
•
[15]Garcia J, Rusu A. An extended-range incremental CT∑ Δ ADC with optimized digital filter[C]//Quality Electronic Design (ISQED), 2012
13th International Symposium on. IEEE, 2012: 179-184.
•
[16]Caldwell T C, Johns D A. Incremental data converters at low oversampling ratios[J]. Circuits and Systems I: Regular Papers, IEEE
Transactions on, 2010, 57(7): 1525-1537.
•
[17]Yu W, Aslan M, Temes G C. 82 dB SNDR 20-channel incremental ADC with optimal decimation filter and digital correction[C]//Custom
Integrated Circuits Conference (CICC), 2010 IEEE. IEEE, 2010: 1-4.
•
[18]Tsang R M, Tucker J C, Melanson J L. Discrete-time delta-sigma modulator with improved anti-aliasing at lower quantization rates:
U.S. Patent 8,130,127[P]. 2012-3-6.
•
[19]Garcia, J.; Rodriguez, S.; Rusu, A., "On Continuous-Time Incremental \Sigma \Delta ADCs With Extended Range," Instrumentation
and Measurement, IEEE Transactions on , vol.62, no.1, pp.60,70, Jan. 2012