Transcript Diapositiva 1

UGR White Rabbit
Contribution
Javier Díaz, José Luis Gutiérrez, Miguel
Jiménez {jda,jlgutierrez,klyone}@ugr.es
University of Granada
Index
•
•
•
•
Web Manager Interface
Finedelay Stand-alone Development
WR 10G Development
UGR White Rabbit-Related Projects (SKA, TIGRIS,
EMC2, etc)
• Conclusions
White Rabbit Switch
WEB MANAGER INTERFACE
WRS Web Interface: Why?
• Ease WRS
• WRS all-in-one display
• No need Management
port
• Terminal emulator
• 1-step remote flashing
• Backup&Restore
configuration files
• Layout for other projects
WRS Web Interface: Development
• HTML
• CSS Styles
– Easy layout customization
• PHP Scripting Language
– Easy programming and
connection to back-end
• Lighttpd server:
– open source, lighter, faster
and better performance than
Apache/thttpd.
shw_ver
wr_phytool
wrs_hal
Back-end
WRS Web Interface: Main Features (info)
WRS Endpoints Info:



master/slave
calibrated/uncalibrated
synchronization status
Dashboard:









Hostname
WRS working mode
IP & MAC addresses
Kernel Version
Firmware Version
WR Date
PPSi Status
SNMP Status
NTP Configuration
WRS Web Interface: Main Features II (setup)
•
•
•
•
•
Network Setup
– DHCP Configuration
– Static IP Configuration
PPSi Setup
– Enable/Disable
– Clock Class & Accuracy settings
Endpoint Mode
– Master/Slave
Vlan Setup
– Create&display Vlans
– Endpoint Vlan configuration
Switch Management
– WRS mode: Master/GrandMaster
– Enable/Disable SNMP
– NTP Server configuration
– Backup&Restore configuration files
(ppsi, sfp, snmp, etc)
•
SFP Calibration Parameters
– Part Number, Alpha, Delta Tx/Rx
•
Endpoint tools
– Enable/Disable calibration transmission
– See/modify registers
•
Endpoint Calibration for
(wrsw_hal.conf):
– WRS Timing Values (PPS Width, NMEA,
mode)
– Each endpoint (Min Rx/Tx, Mac Address,
mode)
•
Loading Binaries:
– New binary file for lm32
– New FPGA bitstream
•
•
•
Terminal emulator
Remote firmware update
Login system
WRS Web Interface: How to use it
Switch on your WRS
Login:
User: admin
Pass: (none)
Provide an IP
to eth0:
-DHCP
-Static IP
Open your browser and
put the eth0 IP Address
WRS Web Interface: What’s next?
•
•
•
•
Feedback from users
Feedback from WR community
Adapt the interface to new changes
Adding new PHP users, groups and views
Missing something?
SPEC100 / SPEC (ALPHA)
FINEDELAY STAND-ALONE
DEVELOPMENT
A stand-alone mode for the FineDelay?
• Can be used as an external granmaster clock reference
– cheaper than a GPS
• No need for a dedicated computer
– One desktop can control several FDs
• In addition to:
– Can be used to debug any core
inside the FPGA.
– Its firmware can be modified onthe-fly
Port to stand-alone
user@pc:~$ insmod
fmc_fine_delay.ko
Stand-alone requirements
• Develop both firmware and gateware to reproduce the non-lineal flow of
the kernel driver
• Using another GCC/Linux API minimizing the impact on the existing
SW/driver.
• Implement a new embedded interface to controll the fine-delay core
12
Stand-alone Implementation
•
GN 4124 Core has been disabled
(unnecessary for stand-alone)
•
Fmc&finedelay drivers adaptation to
a secuential program
• board components initilization
• calibration
•
New lm32 added
• IRQ Slave
• DPBRAM
•
New Timer core:
• Time Counter
• IRQ Timer
•
New UART for debugging
• UART selector
13
Stand-alone Remote Access/Programming
Updating the debugger-LM32 program remotely (Etherbone/CALoE)
eb-cl [-a BASEADDRESS] [-e proto/IPv4] <ram file>
eb-optimizer [-e proto/IPv4] [-w] <BASEADDRESS> <num words> <pattern>
Updating the debugger-LM32 program remotely (RS232)
wrpc-cl.py <PORT> <ram file>
14
Stand-alone FINEDEL status
• Collaboration work between UGR and Seven (6 months interim at
Seven & master thesis of José Jiménez).
• Development validated using SPEC100 board (larger programming
memory)
• SPECv4 (45T FPGA) unstable (latest driver changes + 45T memory
resources constraints). Further test required.
• The extra LM32 processor allows to develop additional
functionalities (on-board programmer using serial port, debugging
& testing, etc…)
• Approach extensible to other FMC projects (TDC, ADCs, etc…)
TIGRIS, EMC2, SKA, …
UGR WHITE RABBIT-RELATED
PROJECTS
National/international projects
• Subcontration from industry:
– TIGRIS (national) and EMC2 (EU Artemis) projects: evolution of WR
technology in the framework of Smart Grid
•
SKA, SADT-SAT activities.
• EU calls participation:
– Goals: 10G WRCORE, PLL control and redundant network mechanisms.
– ASTERICS-Cleopatra (ESFRI call)
– SRT-i32 NID (Fiber Next generation time and frequency dissemination
through optical fibres). EMPIR call (collaboration with metrology labs)
On-going work
10G DEVELOPMENT
Introduction
• White-Rabbit technology is 1G but ...
– This is valid for time transfer but a bit restricted for sharing the
same physical channel on data acquisition applications.
– 10G is more used for telecommunication infrastructures →
compatibility problems.
– Some research facilities requires large bandwidth (ASTERICs
project)
– FPGA allows moving forward. Device cost optimization!
• Time to move towards White-Rabbit 10G?
VC709. The development platform
WRPC for VC709
Hardware
VC709 does not include the
tuneable oscillators/PLL.
HACKING TIME based on
SPEC!
Gateware
• Moving
to Virtex-7, using
GTH!
• Update the UCF file.
• Change some
configuration parameters of
WRPC specially the SoftPLL
and Enpoint ones.
Software
• Adapt I2C topology.
• The EEPROM memory
driver must be changed to
work in the new board.
Clock distribution for SPEC / WR-Switch
SPEC
WR-Switch
WRPC Gateware for VC709
Configuration
(Endpoint,
SoftPLL)
PLLE2_BASE
1. The clock signals come to
the SPEC resources and are
adapted to use them inside
the VC709 board.
2. The PLL primitives have
been updated. The MMCM
components are available in
Virtex-7 FPGA but they are
not used in our design to
reduce the resources
utilization.
SPEC
3. The Spartan-6 GTP primitive
has been replace with
Virtex-7 GTH one.
4. The Endpoint datapath
width must be 16 bits
instead of 8 bits.
5. There is a SoftPLL generic
parameter that must be
changed 
“g_divide_input_by_2”
must be FALSE
IBUFDS_GTE2
GTHE2_CHANNEL
From 1G to 10G White-Rabbit
VC709 board
WRPC for 10G
• A clock redistribution is needed for
the 10 Gigabit Ethernet Technology.
• A new Endpoint component must
be developed for the 10 Gigabit
Ethernet standard.
• The WRPC software must be
adapted as well.
• The SPEC frequency synthetizer IC
must be configured to generate a
clock signal with a frequency of 156
MHz.
Available IP Cores for 10G (Xilinx)
•
•
•
•
•
•
“AXI 10G Ethernet with 1588” --> MAC and PHY layers. Moreover, it provides
mechanisms for the IEEE 1588 standard.
– Non-free
– AXI bus instead of Wishbone
“10 Gigabit Ethernet Media Access Controller (10GEMAC)” --> MAC layer.
– Non-free
“XAUI/DXAUI” --> PMA layer for transceiver of low speed rate < 10 Gbps -->
Multiplexing several channels. We want a real 10G link!!
– Free
“10 Gigabit Ethernet PCS/PMA with FEC/Auto-Negotiation (10GBASE-KR) --> PHY layer
(PCS+PMA).
– Non-Free
“10 Gigabit Ethernet PCS/PMA (10GBASE-R)” --> PHY layer (PCS+PMA)
– Free
– It does not implement Auto-Negotiation!!
Custom implementation for 10GMAC and PCS/PMA --> New Endpoint
10G developments remarks
• 1G White-Rabbit for V7 will be available very
soon!
• 10G still require additional work
• Extra-work:
– Porting the development to Xilinx Vivado.
University of Granada
ONGOING & FUTURE WORK
Ongoing&Future Work (I)
• NIC project with DMA support: available at the end 2014
• Web Manager Interface maintenance
• Development of a Remote Management Tool for switches and
nodes
• WRCORE extension to 10G implementation
– Final characterization of White-Rabbit 1G on V7
– 10G core test
– Porting the development to Xilinx Vivado.
• Software support for WR-ZEN (with 7S)
• QoS: under study the OpenFlow approach
Ongoing&Future Work (II)
• Remote Management Tool: Desktop
application to manage & configure
big WR networks
- Manage White-Rabbit Switches
or WR-ZEN (SNMP)
- Manage stand-alone devices:
- SPEC+ DIO/FineDelay, etc
CALoE
SNMP
Etherbone
Etherbone
Thanks for attending
Javier Díaz Alonso
[email protected]
Principal Investigator
University of Granada
José Luis Gutiérrez
[email protected]
Local & Remote Management Tools
Zynq + Redundant Topologies
Miguel Jiménez
[email protected]
CALoE + Virtex 7 Port
10G Implementation