Transcript Postervorlage - Universidade Federal de Minas Gerais

Algorithms for Leakage Reduction with
Dual Threshold Design Techniques
SoC ‘06
International Symposium on
System-on-Chip
Konrad Engel, Thomas Kalinowski, Roger Labahn, Frank Sill, Dirk Timmermann
Institute of Mathematics, Institute of AMCE University of Rostock
Dual Threshold Voltages
critical path
80
Leakage [nA]
norm.
Performance
100
50
0
1.0V 0.9V
0.8V 0.7V
VDD
Low Vth
High Vth
DTCMOS
40
0
1.0V 0.9V
0.6V
VDD
0.8V
Low Vth
High Vth
0.7V
0.6V
high Vth
low Vth
(slow, low leakage)
(fast, high leakage)
Measured at NAND2 BPTM 65nm Technology
New Algorithms
Definitions
Single and the Multiple Switch Algorithms
• dag G  (V,E) and v V
k-Family Algorithm (k-FA)
• maxdif (G ) : max dif (v ), v V 
(SSA and MSA)
• LVT version of vertex v

• partially ordered set (poset): Qx ,   with
• start with LVT version of (G,x0):x0(v) = 0 for all v
=> Delay: d0(v) Leakage: c0(v)
Qx : v V : x ( v )  0, slack ( v, x )    max dif (G )
• each optimization step:
• HVT version of vertex v


• a subset S  Qx is called a k -family in Qx ,   if
- weight(v) = slack(v,x) – dif(v) + λc(v)
=> Delay: d1(v) Leakage: c1(v)
• d0(v) < d1(v), c0(v) > c1(v)
- SSA: vertex with highest weight switched to
HVT
• cost function of realization (G,x) (x:V →{0,1}):
- MSA: more vertices are switched to HVT
c(G, x ) :  cx ( v ) (v )
there is no chain in  Qx ,   containing more than k
elements from S
• each optimization step: switching all elements of a
maximum weighted k -family where k  max 1,  
• until there are no more candidate vertices
vV
weight ( v )  1  maxdif (G )  dif ( v )   c( v )
• length of a path P = (v0,,…,vk) inside (G,x):
d ( P, x ) :  d x ( v ) (v )
vP
• slack(v,x): how much can v be delayed without
effects on evaluation time of (G,x)
• switch the whole candidate set to HVT
• set of candidates vertices
• critical graph: Gx  Vx , E x  with
C : v V : xv   0 and slack (v, x)  dif (v)
k-Cutset Algorithm (k-CA)
Vx : v V : slack ( v, x )  0, E x : vw  E : v, w Vx and e( v, x )  d x ( v ) ( v )  e( w, x )
• dif(v) = d1(v) – d0(v), c(v) = c0(v) – c1(v)
• then S  Vx is a k -cutset in Gx if every path from a circuit input to a circuit output in Gx has at least k vertices in S
• DTCMOS: find decision function such that
• put
 d(G,x) - d min (G) 
k : 
,
maxdif
(G)


switch vertices in minimum weighted k-cutset in Gx to zero and iterate this until dmin(G) is reached
• continue until the candidate set is empty
d(G,x) = dmin(G,x), c(G,x) is minimal
Simulation Results
Leakage Reduction of ISCAS benchmark circuits
Leakage Reduction [%]
Runtimes (@1.3 GHz Centrino, 512 MB)
time [s]
90
60
30
0
80
60
40
20
0
c432
c499
c880
c1355 c1908 c2670 c3540 c5315 c6288 c7552
c432
c499
c880
c1355 c1908 c2670 c3540 c5315 c6288 c7552
SSA
SSA
MSA
k-FA
MSA
k-FA
k-CA
[1]
k-CA
[1] F. Sill et.al., “Low Power Gate-level Design with MixedVth (MVT) Techniques“,17th SBCCI, 2004.
University of Rostock, Germany
Institute of Mathematics
Institute of Applied Microelectronics and Computer Engineering
Contact: [email protected], [email protected]