Transcript TT&C BWG - unipi.it

MORE Team Meeting
On-Board Calibration System
for the Range Delay of the
BepiColombo KaT
G.Boscagli (ESA-ESTEC)
M.Mascarello (AAS-I)
27th February 2007
27th February 2007
Page 1
Introduction for BepiColombo
KaT On-board Calibration
(for Ranging Delay)
27th February 2007
Page 2
Approach for On-Board Calibration
 The approach hereafter preliminary analysed is based on the idea
of implementing this function directly inside the KaT unit:
Target  Calibration as KaT Internal Unit Function
 The idea is to include inside the KaT unit both the SSPA and the
Diplexer function.
In general more compact solutions improve S/C design (mass,
interfaces routing, etc); it is believed that also calibration
performances should be improved following this approach.
NOTE – In this way the calibration doesn’t take into account the wave-guides
(from-to-antenna) and the antenna itself. They are outside the calibration loop.
Which is the contribution of wave-guides and antenna in the overall end-to-end
ranging budget error? At present it is understood that the main effect to be
considered is related to the input/output mismatching variation due to temperature
variation. This might cause multi-path effects and error in the end-to-end ranging
measurements.
27th February 2007
Page 3
Approach for On-Board Calibration
 For this reason (Calibration as an internal KaT function) the KaT unit must
be commanded (by the on-board computer) in two different modes:
 Nominal Mode: RF link via antenna, unit in coherent mode (down-link coherent
with the uplink both for carrier and ranging signal) when RX in Tracking Mode.
 Calibration Mode: RX and TX in Loop-back Configuration, unit running with the
internal oscillator, RX coherent (in tracking) with the loop-back signal from the TX
 The approach hereafter proposed is based on the use of PN regenerative
ranging, the reasons are:
 The use of this ranging scheme simplifies the calibration scheme in particular for
the ambiguity resolution (when compared with other approaches as the ESA STD
or the NASA Tone Ranging).
Note - The ambiguity must be solved since the KaT loop-back delay (TX-RX) is
expected of the order of microseconds, while the WBRS band should be in the range 520 MHz.
This comment might not be valid anymore in case the group delay variation (versus
environmental conditions and including aging) is inside the WBRS ambiguity resolution.
This is difficult to be predicted at this stage.
 The PN regenerative ranging is already implemented inside the BepiColombo
X/X/Ka Deep Space Transponder, so it can be easily re-used for the KaT unit
simplifying the multi-frequency operation as needed by BepiColombo for plasma
cancellation.
27th February 2007
Page 4
Impact of Calibration on
BepiColombo KaT Front-End
Architecture
NOTE: this section has been written without considering the
current subsystem architecture
27th February 2007
Page 5
Impact of Calibration on KaT Front-End Architecture
Preliminary RF Power Budget (TX Filter neglected)
RF Budget
T2 is indicated as variable attenuator, it might
be commanded for selecting the proper RF
power (at RX input) for calibration: minimum
value around -146 dBm (nominal value around
-125 dBm, TBC) .
TX
2
W
33.01
dBm
TX coupler
30
dB
3.01
dBm
Attenuator- T1
30
dB
-26.99
dBm
Passive Mixer
10
dB
-36.99
dBm
Attenuator- T2
60
dB
-96.99
dBm
RX coupler
50
dB
-146.99
dBm
34 GHz
RX Filter
LNA
Loop-Back Path
RX coupler
T2
To Ant
X
LO @ 2 GHz
Amplifier Gain Control (TBC)
T1
TX coupler
TX Filter
32 GHz
27th February 2007
Amplifier
2 Watt SSPA
Page 6
Impact of Calibration on KaT Front-End Architecture
 According to the proposed approach, the new
circuits/functions to be developed are:
 The functions in the light-blue boxes: 2 GHz LO, T1, T2,
Mixer
 The functions in the light-green boxes: TX coupler, RX coupler
NOTE - The functions indicated in the light-red boxes represent the Diplexer and
they are present in any case. In the current subsystem baseline (see dedicated
slides by AAS-I on this issue), the Diplexer is indicated as external to the KaT;
the advantage of having it integrated inside the KaT unit is clear from a
calibration point of view and for a more compact solution.
 According to the architecture as proposed in the
previous slide, when in calibration mode the loop-back
signal is routed back from the TX to the RX side and to
the antenna as well.
NOTE – It might be useful (TBC) to introduce the control of the TX Power (2
Watt SSPA) to minimise the TX power via antenna when in calibration mode;
question: is the SSPA delay dependant on the selected Gain/Output-Power?
27th February 2007
Page 7
Impact of Calibration on KaT Frequency Plan
 The KaT frequency plan must be carefully studied in order to simplify
the generation of the 2 GHz LO signal and to avoid internal RFI
issues.
NOTE - For instance considering the Cassini KaT frequency plan (next slide) we
observe that the 1st IF chain is almost at the same frequency of the LO signal for
calibration.
 The Cassini KaT turn-around ratio (next slide) is not included in the
current CCSDS/ECSS recommendations for TT&C applications. The
values from the current ECSS-E-50-05B (Radio Frequency and
Modulation, draft issue under public review) are:
 The Ka/Ka turn-around ratio values are under discussion also in
the frame of CCSDS, at present the draft recommendation
(January 2007) is to use 3599/3344 and 3599/3360
27th February 2007
Page 8
Cassini KaT Frequency Plan
AGC LOOP
FILTER
Front-End
Preselector
X
21F
A
315F
Ka-Band
output
Bw =2 MHz
Bw = 80 MHz
L.N.A. & Filter
Ka-Band
input
2nd IF
20F
x3
& Filter
HPLL
294F
to external amplif ier
(TWTA)
F
X
1st IF
294F
AGC
DETECTOR
XTAL Filter
Bw = 15 KHz
X
X
x5
98F
Q-branch
4F
SPLL
x49
Loop
Filter
x4
2F
x2
Lock
Detector
F
0°
90°
VCXO
F  109 MHz
I-branch
Lock Status
Turn-around ratio = 294/315 = 14/15
27th February 2007
Page 9
CURRENT COMMUNICATIONS
SUBSYSTEM BASELINE
(from BepiColombo SRR Data Package)
This section has been provided by AAS-I (Marco Mascarello)
Question: Are there any difficulties (due to on-board baseline
architecture) for implementing the above proposed approach for
calibration?
27th February 2007
Page 10
Communications Subsystem Current baseline
27th February 2007
Page 11
Communications Subsystem (Option KaT Amplifier)
27th February 2007
Page 12
KaT on board calibration including Triplexer
Including a Triplexer inside the KaT, it would be possible to calibrate all the paths till the antenna interface.
From Ka-Band TWTA (X/X/Ka DST)
Ka TRIPLEXER
KaT assembly
34 GHz
RX Filter
To Ant
LNA
coupler
T2
X
LO @ 2 GHz
T1
TX Filter
circulator
27th February 2007
32 GHz
Amplifier
2 Watt SSPA
Page 13
Triplexer (from current BepiColombo SRR Data Package)
 The Ka-Band Triplexer is a 4 port device in charge of splitting input
and output signals. It will consist of a new development for
BepiColombo based on existing technology.
 The splitting will be accomplished by an E-plane trifurcation. Each
sub-band will be selected by an H plane filter. The foreseen useful
bandwidth of the filters will be the following:
 Rx Filter : 50 MHz (TBC) within 34 200 to 34 700 MHz
 Tx1 Filter : 200 MHz (TBC) within 31 800 to 32 300 MHz
 Tx2 Filter : 50 MHz within (TBC) 31 800 to 32 300 MHz
 As for the X-Band diplexer, the mechanical concept will be two
symmetrical pieces. Interfaces will be standard WR28 waveguide
flanges. The estimated dimensions for the assembly are 75 x 45 x
23.1 mm, while the estimated maximum mass should be less than
65 g.
27th February 2007
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Concern
 The above solution based on the Triplxer inside the KaT
unit shows an important drawback:
The Ka-band DST signal is applied to the Antenna
through the KaT unit.
This represents a blocking point !
 Other solution must be addressed, for instance:
1. Keeping the Triplexer external to the KaT unit
(calibration not anymore an internal KaT function).
2. Analysing different mixing approach between DST
and KaT signals at HGA input.
27th February 2007
Page 15
BepiColombo X/X/Ka DST PN
Regenerative Ranging
 1999 JPL
 Balanced Weighted-Voting Tausworthe (v=2 and 4)
27th February 2007
Page 16
Introduction to Pseudo Noise (PN) Ranging Sequence
•
•
The term “Pseudo-Noise (PN) ranging” refers in a strict sense to the use of a
ranging-sequence system in which the ranging sequence is a logical
combination of the so-called range clock-sequence and several PseudoNoise (PN) sequences.
The range clock sequence is the alternating +1 and –1 sequence of period 2
chips.
TC
(a) ranging–sequence waveform
Range Clock Frequency =
 f RC 
•
1
Hz .
2TC
(b) range–clock waveform
A Pseudo-Noise (PN) sequence is a binary 1 sequence of period L whose
periodic autocorrelation function has peak value +L and all (L–1) off-peak
values equal to –1.
27th February 2007
Page 17
Introduction to Pseudo Noise (PN) Ranging Sequence
Example for the introduction of the Titsworth/Tausworthe generation scheme
PN Sequence
Component Sequences
or
Probe Sequences
As an example, considering the following component sequences of period 2, 3 and 5,
respectively (the first period of each sequence is underlined):
Seq. Gen. # 1
Seq. Gen. # 2
Seq. Gen. # 3
Combined by majority logic give the following period-30 sequence:
PN Sequence
27th February 2007
Page 18
Introduction to Pseudo Noise (PN) Ranging Sequence
Example for the introduction of the Titsworth/Tausworthe generation scheme
 Note that the period T of the PN sequence obtained with the
Tausworthe scheme is given by: T  LCM T1 ,T2 ,...,Tm 
with LCM = Least Common Multiple
30 in the above example
Importance of having prime length component sequences
 The correlation of this sequence (considered as +/-1 sequence) with the
component/probe sequences gives the following results:
 Note that 2 + 3 + 5 = 10 operations of correlation are required instead
of the 30 operations needed in the “classical” approach. In fact, only 9
decisions are required because of the antipodal result of the sequence
of period-2 (the clock sequence). Only one of the two operation of
correlation must be performed because the other correlation will be the
negative of the other.
27th February 2007
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Introduction to Pseudo Noise (PN) Ranging Sequence
More in general we can state that:
 The ranging sequence is acquired by the receiver as the result of correlations
between the received sequence and certain ±1 periodic sequences (and their
cyclic shifts) whose periods are divisors of the rangingsequence period and that
we will refer to as probing sequences.
 The probing sequences are related in some manner to the ranging sequence, e.g.,
the ranging sequence might be the sequence resulting from some sort of voting
by the chips of all the probing sequences at the same chip time.
 The probing sequences must have the property that when all these “in-phase”
decisions are correctly made, then these decisions determine the delay (modulo
the ranging sequence period L) in chips of the received ranging sequence relative
to the corresponding model of the ranging sequence. The (one-way) ambiguity
(U) due to the period of the ranging sequence in meters is
f Chip _ Rate
1
1
cL
f RC 

U  c  L  Tc 
= ranging clock frequency
2Tc
2
2
4 f RC
f Chip _ Rate  chip rate
c = speed of the light
For example, with L = 1,009,470 chips and
f RC  106 Hz, U  75,710,000 m or about 75,710 km.
27th February 2007
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The 1999 JPL PN Ranging scheme (Tausworthe scheme)
Titsworth/Tausworthe generation scheme
 The combining logic is based on the following rule: the ranging-sequence chip is a +1
if and only if either C1 has a +1 at that position or all five of the sequences C2, C3, C4,
C5 and C6 have a +1 at that position, or both.
In literature this
sequence can be
indicated also as
JPL 99 or Taus
where the combining logic is
C  C1 C2  C3  C4  C5  C6
 C1, C2, … C6 are the so called Probing Sequences.
27th February 2007
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The 1999 JPL PN Ranging scheme (Tausworthe scheme)
 It is obvious from this combinational rule that the range clock will be strongly
correlated with the ranging sequence, which facilitates locking on to the range clock at
the receiver.
 Since the component sequences C2, C3, C4, C5 and C6 are all PN sequences with
relatively prime periods 7, 11, 15, 19 and 23, respectively, the period of the 1999 JPL
ranging sequence is L =2x7x11x15x19x23 = 1,009,470 chips.
 The probing sequences in the 1999 JPL PN ranging-scheme are the range clock
sequence together with the five component PN sequences.
 The total number of correlation operations required for the probing sequences,
excluding the range clock, is thus 7 + 11 + 15 + 19 + 23 = 75.
27th February 2007
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The 1999 JPL PN Ranging scheme (Tausworthe scheme)
Correlation characteristics and spectrally relevant properties of
the ranging sequence and probing sequences
Residual carrier
Mod index = 0.82 rad-pk
Clock Components
at ±fRC
Chip Rate at
± fChip_Rate = 2.5 Mcps
The spectrum shows a powerful clock component at half the chip rate and below a noisy
floor originating from the combination process with the other probing sequences. The fact the
range clock is strongly correlated with the ranging sequence will facilitate locking on to the
range clock at the receiver. The chip is square-wave shaped.
27th February 2007
Page 23
Weighted-Voting Tausworthe PN Ranging-Sequence Scheme
Select chip value with most votes
The Weighted-Voting Tausworthe sequences are derived from the 1999 JPL PN
Ranging sequence with an apparently small modification on the vote logic.
 The selection of different value for the clock vote (v=2 or 4) provides:
 flexibility in the choice of the strength of the range-clock component in the ranging
sequence
 different level for the power allocated to the clock and the other ranging spectral
components.
v
+1 1
1
+1 +1 +1 1 1 +1 1
1
+1 +1 +1 1 1 1 +1 1 +1 +1 1
1
+1 +1 +1 +1 1 1 1 +1 1 1 +1 +1 1 +1 1
1
+1 +1 +1 +1 1 +1 1 +1 1 1 1 1 +1 +1 1 +1 +1 1 1
1
+1 +1 +1 +1 +1 1 +1 1 +1 +1 1 1 +1 +1 1 1 +1 1 +1 1 1 1 1
C1
C2
C3
C4
C5
C6
6


v C1   Ci 
where the combining logic is C  sign  2
i 2


27th February 2007
Page 24
Balanced Weighted-Voting Tausworthe PN Ranging-Sequence Scheme
The Balanced Weighted-Voting Tausworthe sequences are derived from the
Weighted-Voting Tausworthe sequences (scheme above) with an apparently
small modification on the polarity of some probe sequences.
As the 1999 JPL PN Ranging scheme (Tausworthe scheme) also the Weighted-Voting
Tausworthe PN Ranging-Sequence Schemes (both for v=2 and 4) present a DC component.
A simple way to reduce the imbalance in the ranging sequence (and to produce what we call
the Balanced Weighted-Voting Tausworthe ranging-sequence scheme) is choosing the PN
probing sequences with the following first periods:
C1 = +1 1
C2 = +1 +1 +1 1 1 +1 1
-C3 = 1 1 1 +1 +1 +1 1 +1 1 1 +1
-C4 = 1 1 1 1 +1 +1 +1 1 +1 +1 1 1 +1 1 +1
C5 = +1 +1 +1 +1 1 +1 1 +1 1 1 1 1 +1 +1 1 +1 +1 1 1
-C6 = 1 1 1 1 1 +1 1 +1 1 1 +1 +1 1 1 +1 +1 1 +1 1 +1 +1 +1 +1
Note The key to elimination of imbalance is the fact the negative of a real
sequence has the same autocorrelation function as the original sequence.
27th February 2007
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BepiColombo X/X/Ka DST: Code Phase Acquisition
The current model of
BepiColombo X/X/Ka DST is
programmable and can handle the
different schemes: JPL99, BT2 and
BT4.
The Regenerative Ranging
Channel is composed by:
Code Correlators
CODE CORRELATOR #1
From Carrier
Quadrature
Qc
branch
IN-PHASE
INTEGRATOR
SIGN
C1
CODE GENERATOR #1
+/-1
MID-PHASE
INTEGRATOR
Dismiss
Lock
L
DELAY
CODE CORRELATOR #2
Max.
Search
C2
TIMING
LOGIC
 the Chip Tracking Loop (CTL)
for ranging code clock component
phase and frequency recovery
LOOP
FILTER
NCO
Nominal Chip
Rate
N
 the In-phase Integrator output
is provided to Code Correlators:
Six Correlators running in parallel for
probe sequences (C1,…. C6)
position recovery
Carrier Loop
Error
CODE GENERATOR #2
Dismiss
Lock
CODE CORRELATOR #3
Max.
Search
C3
Dismiss
CODE GENERATOR #3
Chip Tracking Loop
Code Components
Generators Clock
Lock
CODE CORRELATOR #4
C1
Lock Status
 the Down-link Code Generator
(In this case only the JPL99 case is
represented)
Lock
Max.
Search
Max.
Search
C4
Dismiss
CODE GENERATOR #4
C2
Down-Link
Ranging Code
C3
OR
AND
C4
C5
Lock
CODE CORRELATOR #5
Max.
Search
C5
CODE GENERATOR #5
Dismiss
C6
Lock
Down-Link Code Generator
CODE CORRELATOR #6
Max.
Search
C6
REGENERATIVE RANGING CHANNEL
27th February 2007
Dismiss
CODE GENERATOR #6
Page 26
BepiColombo X/X/Ka DST: Chip Tracking Loop (CTL)
The mid-phase integrator output is multiplied by +/-1 in order to provide
the right correction to the loop. In a certain way the multiplication by +/-1
replaces the transition detector typical of a DDTL, considering that the
PN sequence resembles a square-wave.
Filtered Loop Error
Quadrature
Carrier
Branch
Output
CTL NCO Base
Frequency
Scaled Carrier
Loop Error
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BepiColombo KaT Calibration
based on
PN Regenerative Ranging
27th February 2007
Page 28
Impact of Calibration on BepiColombo KaT Baseband Processing
 We need a separate PN code generator on the TX side clocked by the onboard oscillator
 In the current X/X/Ka DST design the TX PN code is generated coherently with
the received up-link PN code (see previous slide).
 The TX PN NCO and the RX PN NCO must be clocked with the same
oscillator, avoiding any timing error between the two signals.
 At the start of the calibration procedure (defined by a strobe signal common
to RX and TX processing functions) the two PN code generators (RX and
TX) must be identically initialised.
 The loop back ranging signal acquired by the RX provides the delay from TX
to RX (Loop-Back Delay).
 The PN code phase acquisition (using the Probe Sequences) is used for
ambiguity resolution
 The phase difference between TX and RX ranging clock provides the accurate
delay measurement
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Impact of Calibration on BepiColombo KaT Baseband Processing
 The phase difference between the RX and TX PN Ranging Clock can be
measured using the filtered phase error loop term of the CTL
α
X
Kd
+
CTL Detector
1/S
X
To RX PN Code Generator
KNCO
RX NCO
β
+
E
B (nominal chip rate)
On-Board Clock
TX NCO
To TX PN Code Generator
27th February 2007
B (nominal chip rate)
CTL second order loop
Page 30
Impact of Calibration on BepiColombo KaT Baseband Processing
K

 Open Loop CTL Transfer Function
G( s)  K d    NCO
s s

 In the X/X/Ka DST the CTL is digitally implemented inside the RX
Digital Section (Ts is the loop sampling time), using the Z transfer
function we have

 T 2  K
s
 NCO1
G( z )  K d   Ts 
1 
1 z  1 z

CTL second order loop:
digital representation
αTs
X
Kd
Ts
+
CTL Detector
X
βTs2
RX NCO
N-BIT
+
E
B (nominal chip rate)
FCLK=1/Ts
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Impact of Calibration on BepiColombo KaT Baseband Processing
 After the transient phase, the error term E provides the
measurement of the delay between the TX and RX ranging clock
signal. In radiant we can write:
F
1
2 clk
E

T

2

E
s
2N
2N
1
E  Ts
 While in time we have:
N
2
 It is evident that for typical loop sampling time of the order of 40
MHz and N=32 bit NCO the phase/time resolution is well below
the required BepiColombo ranging delay accuracy. The calibration
resolution in time due to the digital loop implementation is:
Ts 2 N
 The Probe Sequence acquisition phase and the CTL error term
(E) must be transmitted via telemetry down-link (using the X/X/Ka
DST link). This information (after proper post-processing) can be
used (on-ground) to evaluate the accurate Loop-Back delay.
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Impact of Calibration on BepiColombo KaT Baseband Processing
 Notice that the KaT Ranging Delay (RX => TX) and the Loop
Back Ranging Delay (TX => RX) might be different, this is due
to:
1. The TX/RX different paths (between nominal and calibration mode)
in the Front-End (Attenuators, Mixer, Couplers)
2. Different routing of the signal in the baseband digital processing
(ASIC gates).
 Probably the first contribution could be kept small (and
negligible also under variations of environmental conditions) in
terms of overall error budget. This to avoid further complications
in terms of calibration.
 Also the second contribution (inside the DSP) might be kept
negligible; however if not negligible, the delta (between the KaT
Ranging Delay and the Loop Back Ranging Delay) can be
measured at unit level in the LAB. Notice that this contribution is
almost independent from the temperature since it is related to
the clock drift (Note - the X/X/Ka DST is embarking an OCXO).
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CONCLUSIONS
27th February 2007
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Conclusions
 In order to improve the calibration performances and to
minimise the on-board complexity it is suggested to integrate
inside the KaT unit the SSPA, the Diplexer (*), the RF
Calibration Front-End (Attenuators, Couplers, mixer, LO).
(*) The possibility to integrate the Diplexer/Triplexer is not clear
(under discussion).l
 The use of PN Ranging (as per X/X/Ka DST) simplifies the
calibration function in particular for ambiguity resolution.
 Minor changes are foreseen for the base-band digital signal
processing(*). The approach is to transmit the CTL error term
via TLM link for post-processing at the G/S.
(*) However these have an impact on the current X/X/Ka DST FPGA/ASIC
27th February 2007
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