Transcript Chapter #10: Finite State Machine Implementation

Introduction
Chapter #10: Finite State
Machine Implementation
10-1
Chapter Outline
Introduction
• FSM Design with Programmable Logic
• FSM Design with Counters
• FSM Design with More Sophisticated Logic Devices
10-2
Implementation Strategies
Introduction
• Discrete Gate Logic
Emphasis so far
• MSI Logic (e.g., Counters)
• Structured Logic (e.g., PLA/PAL, ROM)
• Field Programmable Gate Arrays (FPGAs)
Function can be configured "on the fly" or in the field
Flipflops/Registers plus discrete gates on the same chip
10-3
FSM Design with Programmable Logic
Mapping a State Machine into a ROM Implementation
Combinational
Logic
Registers
Output
Function
Inputs
Introduction
Outputs
Block Diagram for
Synchronous Mealy Machine
Next State
Function
State
ROM-based Realization
ROM
A0
Registers
D0
Inputs
Outputs
An-1
Dk-1
An
Dk
An+m-1 Dk+m-1
• Inputs & Current State
form the address
• ROM data bits form the
Outputs & Next State
State
10-4
FSM Design with Programmable Logic
Introduction
Effect of Design Process
Using programmable logic for FSM
- consider state assignment, choice of flip-flops,
and state machine partioning
- complex when mapping a design onto programmable logic
Use partitioning strategies to map state machine onto as few components
as possible
Use D flip-flops or MSI registers for the state
- programmable logic component’s outputs are limited
The kind of ROM is the same regardless of the state assignment
PLA/PAL requires a good state assignment to keep manageable the number
of terms to implement the next state and output logic
10-5
Introduction
FSM Design with Programmable Logic
ROM-based Design
Example: BCD to Excess 3 Serial Converter
Conversion Process
Bits are presented in bit serial fashion
starting with the least significant bit
Single input X, single output Z
BCD Excess 3 Code
0000
0011
0001
0100
0010
0101
0011
0110
0100
0111
0101
1000
0110
1001
0111
1010
1000
1011
1001
1100
10-6
FSM Design with Programmable Logic
BCD to Excess-3 Converter
Present State
S0
S1
S2
S3
S4
S5
S6
Next
X=0
S1
S3
S4
S5
S5
S0
S0
Output
X=0 X=1
0
1
0
1
1
0
1
0
0
1
1
0
-1
State
X=1
S2
S4
S4
S5
S6
S0
--
Introduction
State Transition Table
Reset
0/1
S1
0/1
S0
S2
1/0
0/0,
1/1
0/1
0/0,
1/1
S5
Derived State Diagram
S4
S3
0/0,
1/1
1/0
1/0
S6
0/1
10-7
Introduction
FSM Design with Programmable Logic
BCD to Excess 3 Converter
ROM-based Implementation
ROM Address
X Q2 Q1 Q0
0
0
0 0
0
0
0 1
0
0
1 0
0
0
1 1
0
1
0 0
0
1
0 1
0
1
1 0
0
1
1 1
1
0
0 0
1
0
0 1
1
0
1 0
1
0
1 1
1
1
0 0
1
1
0 1
1
1
1 0
1
1
1 1
ROM Outputs
Z D2 D1 D0
1 0
0 1
1 0
1 1
0 1
0 0
0 1
0 1
1 1
0 1
0 0
0 0
1 0
0 0
X X X X
0 0
1 0
0 1
0 0
1 1
0 0
1 1
0 1
0 1
1 0
1 0
0 0
X X X X
X X X X
1
CLK
1
0
X
converter ROM
Z
X
D2
Q2
D1
Q1
D0
Q0
1
0
9
13
12
5
4
CLK
D
C
B
A
QD
175 QD
QC
QC
QB
QB
1 CLR
\Reset
15
14
10
11
Z
7
6
2
QA
3
QA
Circuit Level Realization
74175 = 4 x positive edge triggered D FFs
Truth Table/ROM I/Os
In ROM-based designs, no need to consider state assignment
10-8
Introduction
FSM Design with Programmable Logic
BCD to Excess-3 Converter
LSB
MSB
Timing Behavior for input strings 0 0 0 0 (0) and 1 1 1 0 (7)
0000
LSB
1100
1110
0101
LSB
10-9
Introduction
FSM Design with Programmable Logic
BCD to Excess 3 Converter
PLA-based Design
State Assignment with NOVA
0
1
0
1
0
1
0
1
0
1
0
1
0
S0
S0
S1
S1
S2
S2
S3
S3
S4
S4
S5
S5
S6
S1
S2
S3
S4
S4
S4
S5
S5
S5
S6
S0
S0
S0
1
0
1
0
0
1
0
1
1
0
0
1
1
NOVA input file
S0 = 000
S1 = 001
S2 = 011
S3 = 110
S4 = 100
S5 = 111
S6 = 101
NOVA derived
state assignment
9 product term
implementation
10-10
FSM Design with Programmable Logic
Introduction
BCD to Excess 3 Converter
.i 4
.o 4
.ilb x q2
.ob d2 d1
.p 16
0 000 001
1 000 011
0 001 110
1 001 100
0 011 100
1 011 100
0 110 111
1 110 111
0 100 111
1 100 101
0 111 000
1 111 000
0 101 000
1 101 --0 010 --1 010 --.e
Espresso Inputs
q1 q0
d0 z
1
0
1
0
0
1
0
1
1
0
0
1
1
-
Espresso Outputs
.i 4
.o 4
.ilb x q2 q1 q0
.ob d2 d1 d0 z
.p 9
0001 0100
10-0 0100
01-0 0100
1-1- 0001
-0-1 1000
0-0- 0001
-1-0 1000
--10 0100
---0 0010
.e
10-11
Introduction
FSM Design with Programmable Logic
BCD to Excess 3 Converter
D2 = Q2 • Q0 + Q2 • Q0
D1 = X • Q2 • Q1 • Q0 + X • Q2 • Q0 + X • Q2 • Q0 + Q1 • Q0
D0 = Q0
Z = X • Q1 + X • Q1
1
CLK 9 CLK
1
0
X
converter PLA
X
Q2
Q1
Q0
Z
D2
D1
D0
1
0
13
12
5
4
175
D
C
B
A
1 CLR
\Reset
15
QD
14
QD
10
QC
11
QC
7
QB 6
QB
2
QA 3
QA
Z
10-12
Introduction
FSM Design with Programmable Logic
BCD to Excess 3 Serial Converter
10H8 PAL: 10 inputs, 8 outputs, 2 product terms per OR gate
D1 = D11 + D12
D11 = X • Q2 • Q1 • Q0 + X • Q2 • Q0
D12 = X • Q2 • Q0 + Q1 • Q0
0 1 2 3
45
89
12 13 16 17 20 21 24 25 28 29 30 31
X
0. Q2 • Q0
1. Q2 • Q0
8. X • Q2 • Q1 • Q0
9. X • Q2 • Q0
16. X • Q2 • Q0
17. Q1 • Q0
24. D11
25. D12
32. Q0
33. not used
40. X • Q1
41. X • Q1
0
1
D2
8
9
D11
16
17
D12
24
25
D1
32
33
D0
40
41
Z
Q2
Q1
Q0
D11
D12
10-13
Introduction
FSM Design with Programmable Logic
BCD to Excess 3 Serial Converter
0 1 2 3
45
89
12 13 16 17 20 21 24 25 28 29 30 31
X
0
1
D2
8
9
D11
16
17
D12
24
25
D1
32
33
D0
40
41
Z
Q2
Q1
Q0
D11
D12
10-14
FSM Design with Programmable Logic
More Advanced PAL Architectures
Introduction
Registered PAL Architecture
Programmable AND array device with on-chip flip-flops associated with
output pins
Useful for implementing synchronous Mealy machines or Moore machines
Positive edge-triggered D flip-flops latch the OR plane outputs
These are gated to the output pins through tri-state inverting buffers
when the OE signal is asserted low
10-15
Introduction
FSM Design with Programmable Logic
More Advanced PAL Architectures
Registered PAL Architecture
Buffered Input
or product term
CLK
OE
Q2 • Q0 + Q2 • Q0
Q2 • Q0
Q2 • Q0
D2
Q2+
Q2+
DQ
Q
Q2+
Q2 • Q0 + Q2 • Q0
X
Q2 Q2
D2 = Q2 • Q0 + Q2 • Q0
Q0 Q0
Negative Logic
Feedback
D1 = X • Q2 • Q1 • Q0 + X • Q2 + X • Q0 + Q2 • Q0 + Q1 • Q0
D0 = Q0
Z = X • Q1 + X • Q1
10-16
FSM Design with Programmable Logic
More Advanced PAL Architectures
Introduction
PLA with Programmable Outputs
CLK
OE
DQ
Q
Buried Registers: decouple
FF from the output pin
- One of XOR’s inputs can be programmed with a connection to ground
- Programmable polarity can help you overcome the limited product term
inputs to the OR gate
- The complement of function in sum of product form may use fewer terms
10-17
FSM Design with Programmable Logic
Advanced PAL Architectures
Introduction
XOR PALs
Contain internal XOR gates whose inputs are fed from AND-OR array
structures
Well suited for computing certain arithmetic functions that would generate
many product terms
Advantage of XOR PALs: Parity and Arithmetic Operations
AB
AB
AB
AB
AB
AB
AB
AB
C
C
C
C
C
C
C
C
D
D
D
D
D
D
D
D
A  B  C  D
AB
AB
A  B  C  D
CD
CD
10-18
Introduction
FSM Design with Programmable Logic
Example of XOR PAL
Example of Registered PAL
INCREMEN
T
INCREMEN
T
1
1
0
FIRST
FUSE
NUMBER
4
8
12
16
20
24
28
32
0
36
0
40
D
Q
23
80
120
FIRST
FUSE
NUMBER
S
Q
2
4
8
12
16
20
24
28
0
32
64
96
128
160
192
224
19
2
160
200
D
240
280
Q
22
256
288
320
352
384
416
448
480
Q
3
320
360
D
400
440
Q
21
512
544
576
608
640
672
704
736
4
D
560
600
Q
20
D
720
760
Q
18
Q
D
Q
17
Q
4
Q
768
800
832
864
896
928
960
992
5
640
680
Q
3
Q
480
520
D
19
Q
D
Q
16
Q
5
6
800
840
D
880
920
Q
1024
1056
1088
1120
1152
1184
1216
1248
18
Q
7
D
Q
15
Q
6
960
1000
D
Q
17
1280
1312
1344
1376
1408
1440
1472
1504
1040
1080
Q
8
1120
1160
D
Q
16
1536
1568
1600
1632
1664
1696
1728
1760
Q
9
D
Q
15
1360
1400
D
Q
1792
1824
1856
1888
1920
1952
1984
2016
14
1520
1560
Q
13
11
INCREMEN
T
0
4
8
12
16
20
24
28
32
14
Q
D
Q
13
Q
8
Q
10
1440
1480
Q
7
1200
1240
1280
1320
D
9
12
11
36
NOTE: FUSE NUMBER = FIRST FUSE NUMBER +
INCREMENT
10-19
FSM Design with Programmable Logic
Introduction
Typical registered PALs have several limitations
An output pin is dedicated to the register even if it is used to hold state
information that is never provided off-chip
- To have buried registers with outputs decoupled from the registers
Output pin carries a different signal
- The outputs may be multiplexed allowing the output pin to be
connected to the combinational output from the array or the
registered from the flip-flop
10-20
Introduction
FSM Design with Programmable Logic
Specifying PALs with ABEL
P10H8 PAL
module bcd2excess3
title 'BCD to Excess 3 Code Converter State Machine'
u1 device 'p10h8';
"Input Pins
X,Q2,Q1,Q0,D11i,D12i
pin
1,2,3,4,5,6;
"Output Pins
D2,D11o,D12o,D1,D0,Z
pin
19,18,17,16,15,14;
INSTATE = [Q2, Q1, Q0];
S0 = [0, 0, 0];
S1 = [0, 0, 1];
S2 = [0, 1, 1];
S3 = [1, 1, 0];
S4 = [1, 0, 0];
S5 = [1, 1, 1];
S6 = [1, 0, 1];
Explicit equations
for partitioned
output functions
equations
D2 = (!Q2 & Q0) # (Q2 & !Q0);
D1 = D11i # D12i;
D11o = (!X & !Q2 & !Q1 & Q0) # (X & !Q2 & !Q0);
D12o = (!X & Q2 & !Q0) # (Q1 & !Q0);
D0 = !Q0;
Z = (X & Q1) # (!X & !Q1);
end bcd2excess3;
10-21
Introduction
FSM Design with Programmable Logic
Specifying PALs with ABEL
P12H6 PAL
module bcd2excess3
title 'BCD to Excess 3 Code Converter State Machine'
u1 device 'p12h6';
2 outputs can have
4 different product
terms
"Input Pins
X, Q2, Q1, Q0
pin
1, 2, 3, 4;
"Output Pins
D2, D1, D0, Z
pin
17, 18, 16, 15;
INSTATE = [Q2, Q1,
S0in = [0, 0, 0];
S1in = [0, 0, 1];
S2in = [0, 1, 1];
S3in = [1, 1, 0];
S4in = [1, 0, 0];
S5in = [1, 1, 1];
S6in = [1, 0, 1];
Simpler equations
Q0]; OUTSTATE = [D2, D1, D0];
S0out = [0, 0, 0];
S1out = [0, 0, 1];
S2out = [0, 1, 1];
S3out = [1, 1, 0];
S4out = [1, 0, 0];
S5out = [1, 1, 1];
S6out = [1, 0, 1];
equations
D2 = (!Q2 & Q0) # (Q2 & !Q0);
D1 = (!X & !Q2 & !Q1 & Q0) # (X & !Q2 & !Q0) #
(!X & Q2 & !Q0) # (Q1 & !Q0);
D0 = !Q0;
Z = (X & Q1) # (!X & !Q1);
end bcd2excess3;
10-22
Introduction
FSM Design with Programmable Logic
Specifying PALs with ABEL
P16R4 PAL (registered PAL)
module bcd2excess3
title 'BCD to Excess 3 Code Converter'
u1 device 'p16r4';
"Input Pins
Clk, Reset, X,
"Output Pins
D2, D1, D0, Z
SREG
S0 =
S1 =
S2 =
S3 =
S4 =
S5 =
S6 =
= [D2,
[0, 0,
[0, 0,
[0, 1,
[1, 1,
[1, 0,
[1, 1,
[1, 0,
D1,
0];
1];
1];
0];
0];
1];
1];
state_diagram SREG
state S0: if Reset then S0
else if X then S2 with Z = 0
else S1 with Z = 1
state S1: if Reset then S0
!OE
pin 1, 2, 3, 11;
else if X then S4 with Z = 0
else S3 with Z = 1
state S2: if Reset then S0
pin 14, 15, 16, 13;
else if X then S4 with Z = 1
else S4 with Z = 0
D0];
state S3: if Reset then S0
else if X then S5 with Z = 1
else S5 with Z = 0
state S4: if Reset then S0
else if X then S6 with Z = 0
else S5 with Z = 1
state S5: if Reset then S0
else if X then S0 with Z = 1
else S0 with Z = 0
state S6: if Reset then S0
else if !X then S0 with Z = 1
end bcd2excess3;
10-23
Introduction
FSM Design with Counters
Synchronous Counters: CLR, LD, CNT
0
Four kinds of transitions for each state:
(1) to State 0 (CLR)
CLR
(2) to next state in sequence (CNT)
(3) to arbitrary next state (LD)
(4) loop in current state
CNT
n+1
n
no
signals
asserted
LD
m
Careful state assignment is needed to reflect basic sequencing
of the counter
10-24
Introduction
FSM Design with Counters
BCD-to-Excess 3 Converter
State Diagram
Reset
0/1
1
0/1
0
4
1/0
0/0,
1/1
0/1
3
0/0,
1/1
Note the sequential nature
of the state assignments
5
2
0/0,
1/1
1/0
1/0
6
0/1
10-25
Introduction
FSM Design with Counters
BCD-to-Excess 3 Converter
Transition Table
Inputs/Current
Next
State
State
X Q2 Q1 Q0 Q2+ Q1+ Q0+
0 0 0 0
0
0
1
0 0 0 1
0
1
0
0 0 1 0
0
1
1
0 0 1 1
0
0
0
0 1 0 0
1
0
1
0 1 0 1
0
1
1
0 1 1 0
0
0
0
0 1 1 1
X X X
1 0 0 0
1
0
0
1 0 0 1
1
0
1
1 0 1 0
0
1
1
1 0 1 1
0
0
0
1 1 0 0
1
0
1
1 1 0 1
1
1
0
1 1 1 0
X X X
1 1 1 1
X X X
Outputs
Z CLR LD
1 1 1
1 1 1
0 1 1
0 0 X
1 1 1
1 1 0
1 0 X
X X X
0 1 0
0 1 0
1 1 1
1 0 X
0 1 1
1 1 1
X X X
X X X
EN
1
1
1
X
1
X
X
X
X
X
1
X
1
1
X
X
C
X
X
X
X
X
0
X
X
1
1
X
X
X
X
X
X
B
X
X
X
X
X
1
X
X
0
0
X
X
X
X
X
X
A
X
X
X
X
X
1
X
X
0
1
X
X
X
X
X
X
CLR signal dominates LD which dominates Count
10-26
FSM Design with Counters
Introduction
BCD-to-Excess 3 Converter
.i 5
.i 5
Espresso Input File
.o 7
.o 7
.ilb res x q2 q1 q0
.ilb res x q2 q1 q0
.ob z clr ld en c b a
.ob z clr ld en c b a
.p 17
.p 10
1---- -0----0-001 0101101
00000 1111---0-01 1000000
00001 1111---11-0 1000000
00010 0111--0-0-0 0101100
00011 00-----000- 1010000
00100 0111---0--0 0010000
00101 110-011
0-10- 0101011
00110 10------11- 1000000
00111 -------11-- 0010000
01000 010-100
-1-1- 1010000
01001 010-101
.e
01010 1111--Espresso Output File
01011 10----01100 1111--01101 0111--01110 ------01111 ------.e
10-27
Introduction
FSM Design with Counters
BCD-to-Excess 3 Converter
CLK
1
0
1
0
excess 3 PLA
X
Reset
X
Q2
Q1
Q0
Z
\CLR
\LD
EN
C
B
A
7
P
10
163
T
RCO 15
2
CLK
6 D
QD 11
5 C
QC 12
4 B
QB 13
3 A
14
QA
9 LOAD
1
D Q
Z
C Q
CLR
Synchronous Output Register
When the state diagram has fewer out-of-sequence jumps, a counter
based implementation can be very effective
10-28
FSM Design with More Sophisticated PLDs
Introduction
Programmable Logic Devices = PLD
PALs, PLAs = 10 - 100 Gate Equivalents
Field Programmable Gate Arrays = FPGAs
• Altera MAX Family
• Actel Programmable Gate Array
• Xilinx Logical Cell Array
100 - 1000(s) of Gate Equivalents!
10-29
Introduction
FSM Design with More Sophisticated PLDs
Altera EPLD (Erasable Programmable Logic Devices)
Historical Perspective:
PALs : same technology as programmed once bipolar PROM
EPLDs : CMOS erasable programmable ROM (EPROM)
erased by UV light low power, high speed
Altera building block = MACROCELL
CLK
Clk
MUX
8 Product Term
AND-OR Array
+
Programmable
MUX's
AND
ARRAY
Output
MUX
Q
I/O Pin
Inv ert
Control
F/B
MUX
Programmable polarity
pad
Seq. Logic
Block
Programmable feedback
10-30
FSM Design with More Sophisticated PLDs
Design with More Sophisticated PLDs
Introduction
Altera EPLDs contain 8 to 48 independently programmed macrocells
Personalized by EPROM bits:
Global
CLK
Clk
MUX
Synchronous Mode
1
Flipflop controlled
by global clock signal
OE/Local CLK
Q
EPROM
Cell
Global
CLK
Clk
MUX
local signal computes
output enable
Asynchronous Mode
1
OE/Local CLK
Q
Flipflop controlled
by locally generated
clock signal
EPROM
Cell
+ Seq Logic: could be D, T positive or negative edge triggered
+ one product term to implement clear function
10-31
FSM Design with More Sophisticated PLDs
Design with More Sophisticated PLDs
Introduction
AND-OR structures are relatively limited
Cannot share signals/product terms among macrocells
Altera solution: Multiple Array Matrix (MAX)
EPM5128:
192 macrocells into
12 LAB
100 MSI or P2210
PALs
Logic
Array
Blocks
(LAB)
(similar to
macrocells)
64
programmable
I/O pins
LAB A
LAB H
LAB B
LAB C
LAB D
LAB G
P
I
A
LAB F
Global Routing:
Programmable
Interconnect
Array
EPM5128:
8 Fixed Inputs
52 I/O Pins
8 LABs
16 Macrocells/LAB
32 Expanders/LAB
LAB E
10-32
FSM Design with More Sophisticated PLDs
Introduction
LAB Architecture
Macrocell
P-Terms
Expander
P-Terms
Expander Terms shared among all
macrocells within the LAB
appear like inputs to macrocells
can use expander terms for multilevel structures
EPLDs based EPROMs : less expensive packaging can be used
crosspoints can be reprogrammed individually
10-33
Introduction
FSM Design with More Sophisticated PLDs
P22V10 PAL
INCREMENT
2904
1
0
0
FIRST
FUSE
NUMBERS
4
8
12
16
20
24
28
32
36
2948
2992
3036
3080
3124
3168
3212
3256
3300
3344
3388
3432
3476
3520
3564
3608
40
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
44
88
132
176
220
264
308
352
396
1 1
1 0
AR
D
Q
23
0 0
0 1
Q
5808
SP
P
R
1
0
5809
OUTPUT
LOGIC
MACROCEL
L
18
P - 5818
R - 5819
6
440
3652
484
528
572
616
660
704
748
792
836
880
OUTPUT
LOGIC
MACROCELL
3696
3740
3784
3828
3872
3916
3960
4004
4048
4092
4136
4180
4224
4268
22
P - 5810
R - 5811
2
924
968
1012
1056
1100
1144
1188
1232
1276
1320
1364
1408
1452
P - 5820
R - 5821
4312
OUTPUT
LOGIC
MACROCELL
4356
4400
4444
4488
4532
4576
4620
4664
4708
4752
4796
4840
21
P - 5812
R - 5813
1496
OUTPUT
LOGIC
MACROCEL
L
16
P - 5822
R - 5823
8
4884
OUTPUT
LOGIC
MACROCELL
4928
4972
5016
5060
5104
5148
5192
5236
5280
5324
20
P - 5814
R - 5815
4
OUTPUT
LOGIC
MACROCEL
L
15
P - 5824
R - 5825
9
5368
2156
2200
2244
2288
2332
2376
2420
2464
2508
2552
2596
2640
2684
2728
2772
2816
2860
5
17
7
3
1540
1584
1628
1672
1716
1760
1804
1848
1892
1936
1980
2024
2068
2112
OUTPUT
LOGIC
MACROCEL
L
OUTPUT
LOGIC
MACROCELL
5412
5456
5500
5544
5588
5632
5676
5720
OUTPUT
LOGIC
MACROCEL
L
14
P - 5826
R - 5827
19
10
P - 5816
R - 5817
SYNCHRONOUS
PRESET
(TO ALL REGISTERS)
5764
11
INCREMEN
T
13
0
4
8
12
16
20
24
28
32
36
40
Supports large number of product terms per output
Latches and muxes associated with output pins
10-34
Introduction
FSM Design with More Sophisticated PLDs
+
rows of interconnect
Anti-fuse Technology:
Program Once
Use Anti-fuses to build
up long wiring runs from
short segments
programmed only once
I/O Buffers, Programming and Test Logic
...
...
...
...
...
...
I/O Buffers, Programming and Test Logic
Logic Module
I/O Buffers, Programming and Test Logic
Rows of programmable
logic building blocks
I/O Buffers, Programming and Test Logic
Actel Programmable Gate Arrays
Wiring Tracks
8 input, single output combinational logic blocks
FFs constructed from discrete cross coupled gates
10-35
Introduction
FSM Design with More Sophisticated PLDs
Actel Logic Module
SOA
S0
Basic Module is a
Modified 4:1 Multiplexer
S1
D0
2:1 MUX
AND :
A=D1 B=SOA 0=D0
SO=S1=0
D1
2:1 MUX
Y
D2
Y=SOA DO+SOA+D1=AB
2:1 MUX
D3
R
SOB
Example:
Implementation of S-R Latch
if R=0 then Q=0
if R=1 then Q=1 if S=0
Q=Q otherwise
"0"
2:1 MUX
"0"
2:1 MUX
Q
"1"
2:1 MUX
S
10-36
FSM Design with More Sophisticated PLDs
Actel Interconnect
Introduction
Logic Module
Horizontal
Track
Anti-fuse
high voltage

bidirection
interconnection
between 2 crossing
wires
Vertical
Track
Interconnection Fabric
Antifuse are placed whenever a horizontal and a vertical wire cross as well as
between adjacent horizontal and vertical wire segments
10-37
Introduction
FSM Design with More Sophisticated PLDs
Actel Routing Example
Logic Module
Input
Logic Module
Output
Logic Module
Input
Jogs cross an anti-fuse
minimize the # of jobs for speed critical circuits
2 - 3 hops for most interconnections
worst may be 4 hops
Logic modules must be carefully placed and then
wired by routing interconnections
10-38
Introduction
FSM Design with More Sophisticated PLDs
Design with More Sophisticated PLDs
Xilinx Logic Cell Arrays
CMOS Static RAM Technology: programmable on the fly!
All personality elements connected into serial shift register
Shift in string of 1's and 0's on power up
IOB
IOB
CLB
IOB
CLB
IOB
Wiring Channels
CLB
CLB
IOB
General Chip Architecture:
• Logic Blocks (CLBs)
• IO Blocks (IOBs)
• Wiring Channels
IOB
IOB
IOB
10-39
Introduction
FSM Design with More Sophisticated PLDs
Xilinx LCA Architecture
slew rate : slow down the output signal
I/O Block
Inputs:
Tri-state enable
bit to output
input, output clocks
Outputs:
input bit
Internal FFs for
input & output paths
Program Controlled Options
OUT
INV
TS
INV
OUTPUT
SOURCE
Pull-up used with
unused IOBs
PASSIVE
PULLUP
Vcc
Enable
Output
PAD
MUX
Out
D
Q
Output
Buffer
R
Direct In
Fast/Slow outputs
5 ns vs. 30 ns rise
SLEW
RATE
Q
D
Registered In
TTL or CMOS
Input Buffer
R
Clocks
Global Reset
10-40
Introduction
FSM Design with More Sophisticated PLDs
Xilinx LCA Architecture
Configurable Logic Block: CLB
2 FFs
5 programmable
muxes
Reset
DIN
Mux
Q1
Any function of
5 Variables
A
B
C
D
E
Global Reset
F
Mux
X
Mux
Y
Combinational
Function
Generator
Q2
G
Mux
Clock
Clock, Clock Enb
D RD
Q
CE
Mux
D RD
Q
CE
Clock
Enable
Independent DIN
output can be registered or direct
10-41
Introduction
FSM Design with More Sophisticated PLDs
Xilinx LCA Architecture
CLB Function Generator
A
B
Q1
A
B
F
Mux
C Mux
D
E
Q2
Q1
Function
of 5
Variables
C
D
E
Mux
Function
of 4
Variables
F
Function
of 4
Variables
G
Mux
Q2
G
Any function of 5 variables
Mux
Q1
A
B
C
D
E
Mux
Mux
Mux
Q2
Two Independent Functions
of 4 variables each
10-42
Introduction
FSM Design with More Sophisticated PLDs
Xilinx LCA Architecture
CLB Function Generator
Q1
A
B
Mux
C
Mux
Function
of 4
Variables
D
Certain Limited
Functions of 6 Variables
E
F
Q2
Mux
Q1
A
B
C
G
Mux
Mux
Function
of 4
Variables
D
Q2
10-43
FSM Design with More Sophisticated PLDs
Introduction
Xilinx Application Examples
5-Input Parity Generator
Implemented with 1 CLB:
F = A xor B xor C xor D xor E
(this is a different parity generator than the one in Chapter 8!)
2-bit Comparator: A B = C D or A B > C D
Implemented with 1 CLB:
(GT) F = A C + A B D + B C D
(EQ) G = A B C D + A B C D + A B C D + A B C D
10-44
Introduction
FSM Design with More Sophisticated PLDs
Xilinx Application Examples
n-Input Majority Circuit
Assert 1 whenever n/2 or greater inputs are 1
5-input Majority Circuit
9 Input Parity Logic
CLB
CLB
7-input Majority Circuit
CLB
CLB
CLB
CLB
n-input Parity Functions
5 input = 1 CLB, 2 Levels of CLBs yield up to 25 inputs!
10-45
FSM Design with More Sophisticated PLDs
Introduction
Xilinx Application Examples
4-bit Binary Adder
A3
A2
B3
S3
S2
C2
CLB
S1
S0
C0
S2
2 x Two-bit Adders (3 CLBs
each) yields 2 CLBs to final
carry out
CLB
S0
S1
S3
Cout
Full Adder, 4 CLB delays to
final carry out
A1 B1 A0 B0 Cin
A3 B3 A2 B2
CLB
C1
B0 Cin
A0
B1
CLB
CLB
CLB
Cout
A1
B2
C2
tradeoffs between
resouces and delay
10-46
Introduction
FSM Design with More Sophisticated PLDs
Xilinx LCA Architecture
Interconnect
Direct
Connections
Direct Connections :
fastest, shortest-distance
form of interconnect
Global Long Line :
used for longer distance conn.
or for signals with a moderate
fanout(not possible to connect
every pins)
Long Line Interconnection :
time critical signals that must
be distributed to many CLBs
with minimal clock skew
Switching Matrix Connections
DI CE A
B
X
C CLB0
K
Y
E D R
DI CE A
B
X
C CLB1
K
Y
E D R
Horizontal
Long Line
Switching
Matrix
Horizontal
Long Line
DI CE A
B
X
C CLB3
K
Y
E D R
DI CE A
B
X
C CLB2
K
Y
E D R
Vertical
Long Lines
Global
Long Line
10-47
FSM Design with More Sophisticated PLDs
Introduction
Xilinx LCA Architecture
Implementing the BCD to Excess 3 FSM
Q2+ = Q2 • Q0 + Q2 • Q0
Q1+ = X • Q2 • Q1 • Q0 + X • Q2 • Q0 + X • Q2 • Q0 + Q1 • Q0
Q0+ = Q0
Z = Z • Q1 + X • Q1
No function more complex than 4 variables
4 FFs implies 2 CLBs
Synchronous Mealy Machine
Global Reset to be used
Place Q2+, Q0+ in once CLB
Q1, Z in second CLB
maximize use of direct & general purpose interconnections
10-48
Introduction
FSM Design with More Sophisticated PLDs
Xilinx LCA Architecture
Implementing the BCD to Excess 3 FSM
Clk
Clk
X
CE
CE
A
CE
DI
B
X
Q2
Q0
FG
DI
Q2
B
C
C
Y
K
Q0
FG
E
Q0
K
X
Q2
Q1
Q0
X
Q1
A
X
FG
Y
Q1
Z
FG
E
D
RES
D
CLB1
RES
CLB2
10-49
Design Case Study
Traffic Light Controller
Introduction
Decomposition into primitive subsystems
• Controller FSM
next state/output functions
state register
• Short time/long time interval counter
• Car Sensor
• Output Decoders and Traffic Lights
10-50
Introduction
Design Case Study
Traffic Light Controller
Block Diagram
Reset
Clk
TS
short time/
long time
counter
TL
F
controller fsm
Reset
C (async)
ST
Next State 2
Output
2
Logic
Car
Sensor C (sync)
Clk
2
2
Encoded
Light
Light
Decoders
Signals
3
3
H
State
Register
10-51
Introduction
Design Case Study
Traffic Light Controller
0
Subsystem Logic
asynchronous
inputs
+
Light
Decoders
Present
D
Q
C
F0
F1
2 A
3 B
1 G
RQ
\Present
1
FG FY FR
debounce switch
Cin
0
Y0
Y1
Y2
Y3
139a
4
5
6
7
1
\Reset
0
0
HG HY HR
+
H0
CLK
H1
Car Detector
1 A
Y0
1
4 B
Y1
3
Y2
1 G
Y3
5
139b
1
1
2
1
09
+
Interval
Timer
CLK
Reset
7 P
10 T 163
1
2 CLK RCO
5
6 D
QD 11
5 C
QC 12
4 B
QB 13
3 A
QA 14
9 LOAD
CLR 1
CLR
TL
TS
ST
10-52
Design Case Study
Traffic Light Controller
Introduction
State Assignment : HG=00, HY=10, FG=01, FY=11
.i 5
.o 7
.ilb c tl ts q1 q0
.ob p1 p0 st h1 h0 f1 f0
.p 8
11-0- 1010000
--010 1000100
0--01 1010000
--110 0110100
--111 0011001
-----0 0000010
---01 0101000
--011 1101001
.e
21 literals
8 unique terms
no 5 input gates, 2 4 input gates
14 gates total
10-53
Design Case Study
Traffic Light Controller
Introduction
Next State Logic
State Assignment: HG = 00, HY = 10, FG = 01, FY = 11
P1 = C TL Q1 + TS Q1 Q0 + C Q1 Q0 + TS Q1 Q0
P0 = TS Q1 Q0 + Q1 Q0 + TS Q1 Q0
ST = C TL Q1 + C Q1 Q0 + TS Q1 Q0 + TS Q1 Q0
HL[1] = TS Q1 Q0 + Q1 Q0 + TS Q1 Q0
HL[0] = TS Q1 Q0 + TS Q1 Q0
FL[1] = Q0
FL[0] = TS Q1 Q0 + TS Q1 Q0
PAL/PLA Implementation:
5 inputs, 7 outputs, 8 product terms
PAL 22V10 -- 11 inputs, 10 prog. IOs, 8 to 14 prod terms per OR
ROM Implementation:
32 word by 8-bit ROM (256 bits)
Reset may double ROM size
10-54
Introduction
Design Case Study
Traffic Light Controller
Next State Logic
Counter-based Implementation
HG=00 HY=01 FG=10 FY=11
HG
TL•C / ST
HY
TS / ST
FG
TL+C / ST
FY
TS
TL
\C
TL
C
1 GA
3 A3
4 A2
5 A1
6 A0
13
12
11
10
B3
B2
B1
B0
15 GB
2 x 4:1 MUX
153
YA 7
YB 9
S1 SO
2 14
ST
+
7
10 P 163
T
15
2 CLK RCO
6
5
4
3
D
C
B
A
QD
QC
QB
QA
11
12
13
14
Q1
Q0
9 LOAD
\Reset 1 CLR
TTL Implementation with MUX and Counter
TS / ST
Can we reduce package count by using an 8:1 MUX?
ST = Count
10-55
Introduction
Design Case Study
Traffic Light Controller
Next State Logic
Counter-based Implementation
Dispense with direct output functions for the traffic lights
Why not simply decode from the current state?
HG HY HR
1
1 G
Q1
Q0
3B
2A
Y3
Y2
Y1
Y0
0
0
FG FY FR
0
0
1
7
6
5
4
139a
ST is a Synchronous Mealy Output
Light Controllers are Moore Outputs
10-56
Design Case Study
Introduction
Traffic Light Controller
LCA-Based Implementation
Discrete Gate Method:
None of the functions exceed 5 variables
P1, ST are 5 variable (1 CLB each)
P0, HL1, HL0, FL0 are 3 variable (1/2 CLB each)
FL1 is 1 variable (1/2 CLB)
4 1/2 CLBs total!
10-57
Introduction
Design Case Study
Traffic Light Controller
LCA-Based
Implementation
TL C TS
TS
TS
Q0
Placement of
functions selected
to maximize the
use of direct
connections
Steps
1) map functions onto
CLBs
2) minimize the amount
of inter CLB routing
DI CE A
B
X
C F0
K
Y
E D R
TL
DI CE A
B
X
C
K
Y
E D R
F1
Q0
Q1
Q0
TS
Q1
DI CE A
B
X
C Q1
K
Y
E D R
Q0
Q1
TS
DI CE A
B
X
C
K
Y
E D R
H1
H0
C
Q1
TL
TS
C
Q0
DI CE A
B
X
C ST
K
Y
E D R
DI CE A
B
X
C
K
Y
E D R
10-58
Design Case Study
Introduction
Traffic Light Controller
LCA-Based Implementation
Counter/Multiplexer Method:
4:1 MUX, 2 Bit Upcounter
MUX: six variables (4 data, 2 control)
but this is the kind of 6 variable function that can be
implemented in 1 CLB!
2nd CLB to implement TL • C and TL + C'
But note that ST/Cnt is really a function of TL, C, TS, Q1, Q0
1 CLB to implement this function of 5 variables!
2 Bit Counter: 2 functions of 3 variables (2 bit state + count)
Also implemented in one CLB
Traffic light decoders: functions of 2 variables (Q1, Q0)
2 per CLB = 3 CLB for the six lights
Total count = 5 CLBs
10-59
Chapter Summary
Introduction
• Optimization and Implementation of FSM
State Reduction Methods: Row Matching, Implication Chart
State Assignment Methods: Heuristics and Computer Tools
• Implementation Issues
Choice of Flipflops
Structured Logic Methods
ROM based
PLA/PAL based
Jump Counter Methods
Sophisticated PLDs: Altera, Actel, Xilinx
10-60