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COMBINATIONAL
LOGIC
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Overview
Static CMOS
Conventional Static CMOS Logic
Ratioed Logic
Pass Transistor/Transmission Gate Logic
Dynamic CMOS Logic
Domino
np-CMOS
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Combinational vs. Sequential Logic
In
Logic
In
Circuit
Out
Logic
Out
Circuit
State
(a) Combinational
Output = f(In)
Digital Integrated Circuits
(b) Sequential
Output = f(In, Previous In)
Combinational Logic
© Prentice Hall 1995
Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Static CMOS
VDD
In1
In2
In3
PUN
PMOS Only
F=G
In1
In2
In3
PDN
NMOS Only
VSS
PUN and PDN are Dual Networks
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
NMOS Transistors in Series/Parallel
Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A
B
X
Y
Y = X if A and B
A
X
B
Y
Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
PMOS Transistors in Series/Parallel
Connection
PMOS switch closes when switch control input is low
A
B
X
Y
Y = X if A AND B = A + B
A
X
B
Y
Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Complementary CMOS Logic Style Construction (cont.)
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Example Gate: NAND
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Example Gate: NOR
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Example Gate: COMPLEX CMOS GATE
VDD
B
A
C
D
OUT = D + A• (B+C)
A
D
B
Digital Integrated Circuits
C
Combinational Logic
© Prentice Hall 1995
4-input NAND Gate
Vdd
VDD
VDD
In1
In2
In3
In4
Out
In1
In2
Out
In3
Out
In4
GND
In1 In2 In3 In4
GND
In1 In2 In3 In4
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Standard Cell Layout Methodology
metal1
VDD
Well
VSS
Routing Channel
signals
Digital Integrated Circuits
polysilicon
Combinational Logic
© Prentice Hall 1995
Two Versions of (a+b).c
VDD
VDD
x
x
GND
a
c
b
(a) Input order {a c b}
Digital Integrated Circuits
GND
a
b
c
(b) Input order {a b c}
Combinational Logic
© Prentice Hall 1995
Logic Graph
VDD
x
b
j
c
c
a
PUN
i
x
VDD
x
b
c
j
a
PDN
i
GND
a
Digital Integrated Circuits
b
Combinational Logic
© Prentice Hall 1995
Consistent Euler Path
x
c
i
x
b
VDD
a
j
GND
{ a b c}
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Example: x = ab+cd
x
x
c
b
VDD
x
a
c
b
VD D
x
a
d
GND
d
GND
(a) Logic graphs for (ab+cd)
(b) Euler Paths {a b c d}
VD D
x
GND
a
b
c
d
(c) stick diagram for ordering {a b c d}
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Properties of Complementary CMOS Gates
High noise margins:
VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under the appropriate scaling conditions)
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Properties of Complementary CMOS
Gates
High noise margins:
VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under the appropriate scaling conditions)
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Transistor Sizing
• for symmetrical response (dc, ac)
• for performance
VDD
B
12
C
12
6
A
Input Dependent
Focus on worst-case
D
6
F
A
D
1
B
Digital Integrated Circuits
2
2 C
2
Combinational Logic
© Prentice Hall 1995
Propagation Delay Analysis - The Switch
Model
RON
=
VDD
VDD
Rp
Rp
A
B
F
F
A
CL
Rn
B
Rp
CL
Rn
A
(a) Inverter
Rp
Rp
B
A
Rn
VDD
(b) 2-input NAND
A
F
Rn
Rn
A
B
CL
(c) 2-input NOR
tp = 0.69 Ron CL
(assuming that CL dominates!)
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
What is the Value of Ron?
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Numerical Examples of Resistances for 1.2mm
CMOS
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Analysis of Propagation Delay
VDD
Rp
A
1. Assume Rn =Rp = resistance of minimum
sized NMOS inverter
Rp
B
F
Rn
B
Rn
A
CL
2. Determine “Worst Case Input” transition
(Delay depends on input values)
3. Example: tpLH for 2input NAND
- Worst case when only ONE PMOS Pulls
up the output node
- For 2 PMOS devices in parallel, the
resistance is lower
tpLH = 0.69Rp CL
2-input NAND
4. Example: tpHL for 2input NAND
- Worst case : TWO NMOS in series
tpHL = 0.69(2Rn)CL
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Design for Worst Case
V DD
VDD
1
A
1
F
2
B
CL
4
C
4
2
A
B
B
D
2
F
A
2
A
D
2
1
B
2C
2
Here it is assumed that Rp = Rn
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Influence of Fan-In and Fan-Out
on Delay
VDD
A
B
C
D
Fan-Out: Number of Gates Connected
2 Gate Capacitances per Fan-Out
A
B
C
D
FanIn: Quadratic Term due to:
1. Resistance Increasing
2. Capacitance Increasing
(tpHL )
tp = a1 FI + a2 FI 2 + a3 FO
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
tp as a function of Fan-In
4.0
tpHL
tp (nsec)
3.0
2.0
tp
quadratic
1.0
linear
0.0
1
3
5
fan-in
7
tpLH
9
AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Fast Complex Gate - Design
Techniques
• Transistor Sizing:
As long as Fan-out Capacitance dominates
• Progressive Sizing:
Out
InN
MN
CL
M1 > M2 > M3 > MN
In3
M3
C3
In2
M2
C2
In1
M1
C1
Digital Integrated Circuits
Distributed RC-line
Can Reduce Delay with more than 30%!
Combinational Logic
© Prentice Hall 1995
Fast Complex Gate - Design Techniques
(2)
• Transistor Ordering
critical path
critical path
CL
In3
M3
In2
M2
C2
In1
M1
C1
(a)
Digital Integrated Circuits
CL
In1
M1
In2
M2
C2
In3
M3
C3
(b)
Combinational Logic
© Prentice Hall 1995
Fast Complex Gate - Design Techniques
(3)
• Improved Logic Design
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Fast Complex Gate - Design Techniques
(4)
• Buffering: Isolate Fan-in from Fan-out
CL
CL
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
Example: Full Adder
VDD
VDD
Ci
A
A
B
B
A
B
Ci
A
B
VDD
X
Ci
Ci
A
S
Ci
A
B
B
VDD
A
B
Ci
Co
A
B
Co = AB + C i(A+B)
28 transistors
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995
A Revised Adder Circuit
V DD
VDD
A
B
A
V DD
A
B
B
Ci
B
Kill
"0"-Propagate
A
Ci
Ci
Co
S
Ci
A
"1"-Propagate
Generate
A
B
B
A
B
Ci
A
B
24 transistors
Digital Integrated Circuits
Combinational Logic
© Prentice Hall 1995