RAMP Architecture & Description Language
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Transcript RAMP Architecture & Description Language
RAMP: Architecture, Language
& Compiler
http://ramp.eecs.berkeley.edu
Greg Gibeling, Andrew Schultz, Krste Asanovic
Contact: [email protected]
RAMP Retreat, BWRC, 20 January 2006
7/17/2015
RAMP Architecture, Language & Compiler
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RAMP Design Framework Overview
CPU
CPU
CPU
Interconnect
Network
DRAM
RDL Compiled to
FPGA Emulation
CPU
Target System: the machine
being emulated
• Describe structure in RAMP
Description Language (RDL)
• Describe behavior of each leaf
unit in favorite language (Verilog,
VHDL, Bluespec, C/C++, Java)
RDL Compiled to
Software Simulation
Host Platforms: systems
that run the emulation or
simulation
2VP70
FPGA
2VP70
FPGA
• Can have part of target
mapped to FPGA
emulation and part mapped
to software simulation
2VP70
FPGA
2VP70
FPGA
2VP70
FPGA
BEE2 Host Platform
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Workstation Host Platform
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RAMP Target Model (1)
Port
Sending Unit
Receiving Unit
Channel
Port
Units communicating over channels
Units
Large pieces of functionality, >10,000 Gates
e.g., Processor + L1$
Leaf units implemented in a “host” language
Channels
Unidirectional
Point-to-point
FIFO semantics
Unknown latency and buffering (fixed when system instantiated)
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RAMP Target Model (2)
Transaction-style semantics for unit
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Read 0/1 messages from each input
Perform some action
Write 0/1 messages to each output
Units MUST be latency insensitive
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Target Model - Units
Inside edge
Ports connect units to
channels
__A_READ
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12b
__A_READY
Port “A”
__Start
__Done
Allows for variable
number of host cycles
per target cycle
__Done
A
FIFO signaling
Hardware or Software
Target cycle control
__Start
1b
C
Unit
__C_READY
32b
B
__B_READ
__C_WRITE
Port “C”
__B_READY
Port “B”
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Target Model – Channel (1)
Channel semantics
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Each channel carries arbitrary set of
message types, statically determined
Ordered delivery
Debugging through monitoring & injection
Provides for cross-platform simulations
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Target Model – Channel (2)
Channel parameters for timing-accurate simulations
Bitwidth (in bits per target clock cycle)
Latency (in target clock cycles)
Buffering (in either fragments or messages)
Fragments (one target clock cycle’s worth of data)
Smaller than messages
Convey the simulation time through idles
32b
32b
32b
Bitwidth
Latency
Buffering
Channel
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Target Model – Channel (3)
Sending Unit
Receiving Unit
Message (40b)
Channel
8b
8b
8b
8b
8b
8b
Fragment (8b)
Fragmentation
Messages may be larger
than fragments
Channels carry (per target
cycle):
Timing Model
Zero fragments still
indicates passage of time
Implement outside of the
units
Zero
or one fragments
Between zero and one
messages
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Target Model - Debugging
Channel model + target time model supports:
Monitoring
Single-stepping
Target time can be paused or slowed down
Simulation steering
All communication over channels can be
examined and controlled
Inject messages into channels
Mixed-mode emulation/simulation
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Can move some units into software simulation
Cross-platform communication hidden by RDL
compiler (RDLC)
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Host Model
Host α (Hardware/FPGA)
Library
(Output)
Outside Edge
Cross-platform
Outside Edge
Link A
(Channel A)
Wrapper 1
(Unit 1)
Link B
(Channel B)
Wrapper 2
(Unit 2)
Link C
(Channel C)
Link F
(Channel F)
Link G
(Channel G)
Link H
(Channels
D & G)
RS232
Host β
(Misc. Platform)
Link E
(Channel E)
Library
(Input)
Link D
(Channel D)
Link I
(Channels
E & F)
TCP/IP
Host γ (Workstation)
Link K
(Channel E)
Link J
(Channel F)
Wrapper 3
(Unit 3)
Link L
(Channel H)
Units
implemented in
many languages
Library units for I/O
Links implement channels
Links
Can
be mapped to
anything that transmits
data (e.g.,FPGA wires,
Ethernet, Carrier Pigeon)
Library
(Debug)
Outside Edge
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Host Model – Wrapper (1)
Outside Edge
State & Control
__Start
Timing,
Unpacking &
Buffer
Link A
__Done
Unit
Port A
Timing,
Unpacking &
Buffer
Link B
Control & Status
Inside Edge
Buffer,
Packing &
Timing
Link C
Buffer,
Packing &
Timing
Link D
Port C
Port B
Port D
Inside Edge
Wrapper
Outside Edge
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Host Model – Wrapper (2)
Inside Edge
Wrapper provides this interface to unit
Clean, mostly free of implementation
Outside Edge
Each host language needs language-specific version of
interface
Implementation dependant
Deals with physical links
RDLC generates the wrapper and all of the links
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Uses plugins for easy extensibility to add new host
languages or new link types
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Host Model - Link
Typically Three Components
Packing & Unpacking
Timing Model
Physical Transport
Wrapper
Message Register
Wrapper
Timing Model
Link
Unit
Unit
RDLC Plugin
Unpack Logic
Packing Logic
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RDL (1)
“RAMP Description Language”
General process network system
description language
Compiler includes back-end extensibility
Links, other toolflows, external signals
Does NOT include or examine the
functionality of leaf units!
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RDL (2)
Hierarchical Namespaces
RDL Target Constructs
Channels, Messages and Port types
Units include instances, inputs, outputs and connections
RDL Host Constructs
Declarations can be external to a namespace
Replaces “preprocessing”
Allows for communal development
One platform per board or computer
Platforms include an implementation language
Hierarchy allows for, eg. A board with many FPGAs
RDL Mappings
Hierarchy allows for “compile one, run many”
Allows specific units and channels to be precisely mapped
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RDL Example (1)
232 - 1
Up/Down Counter
•••
Push button input
4-bit LED output
Utility as example
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Proof of concept
Simple language
example
Hands on demo
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1/2
0/1
1
1/1
0/0
0
0/0
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RDL Example (2)
unit {
input bit[1] UpDown;
output bit[32] Count;
}
Counter;
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RDL Example (3)
UpDown
Boolean
Input
Value
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1b
Value
32b
Counter
Display
7Seg
Count
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RDL Example (4)
unit {
instance IO::BooleanInput
instance Counter
instance IO::Display7Seg
channel
{
channel
{
}
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BooleanInput;
Counter;
Display7Seg;
fifopipe[1, 1, 1] InChannel
BooleanInput.Value -> Counter.UpDown };
fifopipe[32, 1, 1] OutChannel
Counter.Count -> Display7Seg.Value };
CounterExample;
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RDL Example (5)
channel … InChannel { BooleanInput.Value -> Counter.UpDown };
instance IO::BooleanInput BooleanInput(InChannel);
channel … InChannel;
instance IO::BooleanInput BooleanInput(Value(InChannel));
channel … InChannel;
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RDL Example (6)
platform {
language
default link
engine
}
"verilog";
“RegisterLink";
“XUPEngine”;
XUP;
map {
platform XUP
BasePlatformInst;
unit CounterExample BaseUnitInst;
XUPCounter;
}
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RDLC Toolflow
Development Steps
Leaf-Unit Implementation
RDL unit descriptions
RDLC generates shell code in a specific language
(Verilog, Java…)
Researcher adds implementation code
RDL system design
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Specify connectivity between leaf units in target
Specify channel parameters (latency, BW, buffers)
Specify mapping of units and channels to host
resources (FPGAs, comm links, …)
RDLC generates complete implementation code
Includes all links, instantiates all unit shells
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RDLC Back End
Language Families
Hardware
Software
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Verilog – Completely finished
VHDL – Trivial addition
Bluespec planned
Java in progress
C/C++ planned
RDL / UTL?
Your language here?
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State of the Project
Working hardware implementation!
Compiled RDL to Verilog
Tested on a CaLinx2 and XUP Board
Java and BEE2 should be done before Feb 1, 2006
RDL & RDL Compiler
RDL is stable
Working compiler, written in java
Powerful parser & output generators
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Some advanced features are in flux
Ready for use!
Easily extensible
Software (Java) back end almost complete
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Future Work
RDL & RDLC Features
Language Features
Significant additions to back end
Languages, platforms, links
Debugging automation
Documentation
Generated code, port arrays and compile time parameters
Architecture, Language & Compiler Technical Report
Complete compiler internals documentation
Automated Testing
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Regression tests for the compiler
Automated test code generation for links and units
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Website & Community
http://ramp.eecs.berkeley.edu
Planned Features
Wiki – Certainly not JSPWiki
CVS Repository
Mailing list control and archives
Communal project listings
Ideas, Comments & Requests
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[email protected], CC: [email protected]
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