Transcript Document

C.A.D.: Bookshelf
June 18, 8:00am-11:00am
Outline
• Review: [some of] bookshelf objectives
• Where we want to go vs what we have now
• Invited presentations
– Herman Schmit, CMU
– Paul Villarrubia, IBM Technology Group
• On-going work
• Current challenges
• Future foci ?
Review: [some of] our objectives
• to provide benchmarking infrastructure
relevant for
– research
– publishing
– industrial use
• offer high-qualify design tools
– preferably open-source
• integrate design tools into tool flows
Where we are now
• So far, mainly focused on physical design
• Available now
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partitioning, floorplanning and placement benchmarks
floorplanner in Java (no source?)
partitioners (MLPart, hMetis)
placers (Capo, Dragon, Feng Shui)
a global router (Labyrinth)
a DB with LEF/DEF parsers and PERL/Tcl/Python
interfaces
– scan chain slot with codes
– RSMT/RMST and BST slot with codes, etc
Where we are now (cont’d)
• Know-how regarding integration with
Cadence and IBM P&R tools
• Links to lots of related general-purpose
goodies
– network-flow solvers
– LP and non-linear solvers
– etc, etc...
We need
• Feedback from the industry and use by the
industry
• More integration, esp. with commercial
tools
• Wider participation and adoption
• Need to refine future focus
Industrial
participation/requirements
and vertical benchmarking
• Paul Villarrubia, IBM
– "An overview of important features for industrial
placement problems"
– Issues: relevant benchmarks and industrial adoption
• Herman Schmit, CMU
– "The Vertical Benchmarking Project at CMU"
– Issues: relevant benchmarks and design tool integration
On-going work
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Ivan Kourtev: optimal clock skew scheduling
C.-K. Cheng: interconnect delay/timing analysis
John Lillis: SITS
Integration and comparisons with commercial
tools
– Cadence Pearl, WarpRoute (UCLA, UMich)
• e.g., CapoT > Pearl > WarpRoute > Pearl
– IBM ChipBench (UMich, IBM)
• e.g., CapoT > EinsTimer > XRouter > EinsTimer
On-going work (cont’d)
• “Simple" (but not easy) benchmarks w/o all
bells and whistles
– solvable with both commercial and academic
tools
– can give apples-to-apples comparisons
– WL-driven and timing-driven placement
(UCLA, UMich)
– routing benchmarks (UMich)
On-going work (cont’d)
• New tools
– an open-source floorplanner in C++ (UMich)
– more versatile open-source routing tools (UMich,
SUNY, etc)
– UCSD is committed to filling in special engines
(clock, power, test, area fill, etc.)
that are needed to get reasonably complete layouts
Discussion: current challenges
• “Separating" global and detail routing (data format,
evaluations, at least one engin for each)
• “Merging" floorplanning and large-scale placement
• Correlating and anti-correlating
– placement wirelength with routability and routed WL
– placement wirelength with timing objectvies
– formulating and validating "simple"/clean design metrics
and optimization objectives for consistent research in
multiple groups (e.g., the overflow metric used by Majid
Sarrafzadeh's group)
Future foci ?
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More attention to data-modeling ?
Fully open-source CAD design flows?
Comprehensiveness
Formulations of open problem submitted by the
industry ?
– remember the "Top-ten list for Physical Design" @ ISPD ?
• More formal and automated interface
– peer reviews for some of bookshelf content
– hit statistics
• Lobbying for an official status with DAC ?
Future foci(?) cont’d
• “Same old"
– more benchmarks ?
– better tools ?
– more empirical comparisons ?
Conclusions…