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SaberDesigner for
Board Level Design
1
#1
7/17/2015
SaberDesigner Overview
SaberSketch
Schematic
Capture
Frameway
Integrations
SaberGuide Interface
Saber
Simulator
Mentor Graphics
Viewlogic
Mast Modeling
Language
AIM Language
SaberScope
Plotting &
Measurement
Package
Cadence
Model Libraries
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3rd-Party Tool
Integrations
Analogy Model Libraries
Standard Template Library
• Extensive number of generic templates (primarily electrical)
DX Component Library (DX OCL)
• Analogy Component Library name (OCL) changed to DX OCL (Optional
•
Component Library)
8000+ mixed-signal, mixed-technology models capable of advanced analyses
(Monte Carlo, Stress, Sensitivity)
SL Component Library (SL OCL)
• 8500+ Semiconductor components
• Developed using manufacturer’s datasheets
• Utilizes macro-model technology
• Reduces the need for in-house model development
Optional Template Library (OTL)
• Contains all the non-electronic Saber templates
• New building blocks added for Telecommunications design (modulators, filters,
noise sources, PLL’s, etc…)
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Audio Example
Discovering Saber with an Example:
Audio Circuit
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Audio Test System
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System: Test Tone Processing
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Test Tone Processing
Generate complex test tones
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System: A/D Converter
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Analog-to-Digital Converter
Digitize analog test signal inputs for DSP
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Relaxation Oscillator
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Oscillator: Hierarchy
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Oscillator: mos primitives
All analog hierarchical circuit (IC-oriented)
Inverter
Nand Gate
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System: Divide by 8 (counter)
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Divide By 8 Circuitry
Divide 40KHz clock to set ADC sample rate
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System: DSP
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Digital Signal Processor
Resonance compensation; sound effects
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System: RLC Filter
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RLC Filter
Filter digital sampling noise
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RLC MC Statistical Summary
_statistics=maximum
1.3
vout
_statistics=median
1.1
_statistics=mean
(V)
0.9
_statistics=minimum
0.7
0.5
0.3
0.1
0.0
500u
0.001
0.0015
0.002
0.0025
t(s)
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0.003
0.0035
0.004
0.0045
0.005
RLC Overshoot (from MC)
0.285
Over(vout)
0.275
(V)
0.265
0.255
0.245
0.235
0.225
0.0
10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 100.0
_run(-)
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RLC Histogram (of Overshoot)
RLC Histogram from Overshoot Measurements
(1) Over(vout)(V)
14.0
count
13.0
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
0.22
0.225 0.23
0.235 0.24
0.245 0.25
0.255 0.26
Over(vout)(V)
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0.265 0.27
0.275 0.28
0.285
RLC Overshoot, r.r1 Correlation
0.285
Over(vout)
0.275
(V)
0.265
0.255
0.245
0.235
0.225
92.0 94.0
96.0
98.0 100.0 102.0 104.0 106.0 108.0 110.0
rnom(r.r1)()
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RLC Sensitivity Report
Sensitivity Analysis Report
Fri Apr 19 20:03 96
.0 Build 41 on 02-Feb-96.17:53:05 Copyright 1986-1995 Analogy, Inc.
-------------------------------------------------------------------------------Sensitivity Analysis Parameters
-------------------------------------------------------------------------------Date of Sensitivity Analysis: Fri Apr 19 17:13 96
Source File:
ex_rlc
Sensitivity Parameter List:
r.r1/rnom r.r2/rnom c.c1/c
l.l1/l
Sensitivity Body Commands:
dc
tr (te 5m, ts 10n, mon 100, ter 100u, pf tr_sens)
meas over (cn vout, pfin tr_sens
-------------------------------------------------------------------------------Sensitivity Report Options
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------Sensitivity of Overshoot of vout in pfile tr_sens
-------------------------------------------------------------------------------Nominal Value = 253.67m
Instance
Part
Type
r.r1
l.l1
c.c1
r.r2
resistor
inductor
capacitor
resistor
Minimum sensitivity magnitude to report: 0
Report sorted by:
Value
Sensitivity normalization:
Normalized
Normalization threshold:
100E-15
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Parameter
Name
rnom
l
c
rnom
Nominal
Value
100
25m
1u
1k
Sensitivity Bar-chart
-1.14
0.439
-0.437
0.285
--------------
System: Power Amplifier
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Power Amplifier
Amplify signal to drive speaker
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Transient Response (5V Input)
12.0
vload
vin
8.0
(V)
4.0
0.0
-4.0
-8.0
-12.0
0.0
0.005
0.01
0.015
0.02
0.025
0.03
t(s)
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0.035
0.04
0.045
0.05
Stress Analysis Report
Stress Analysis Report
Mon Apr 22 15:23 96
.0 Build 41 on 02-Feb-96.17:53:05 Copyright 1986-1995 Analogy, Inc.
-------------------------------------------------------------------------------Stress Analysis Parameters
-------------------------------------------------------------------------------Date of Stress Analysis: Mon Apr 22 15:23 96
Source File:
ex_pwramp
Data File:
ex_pwramp.d1.tr
Xrange:
all
Sliding average window:
1E-2
Derating File:
derating.file
Stress Measure List:
/...
-------------------------------------------------------------------------------Stress Report Options
-------------------------------------------------------------------------------Minimum stress ratio to report:
0
Report sorted by:
Value
Undefined stress ratings reported:
No
Non Applicable stress ratings reported: No
-------------------------------------------------------------------------------Stress Table
--------------------------------------------------------------------------------
Instance
Derated
SM Name
q_3p.q1
r.re
r.re
r.r1
r.r1
q_3p.q1
q_3p.q1
xfr.x1
xfr.x1
r.rload
r.rload
r.rload
q_3p.q1
xfr.x1
c.cin
r.r2
r.r2
xfr.x1
r.rsrc
r.rsrc
xfr.x1
xfr.x1
vcemax
pdmax
pdavg
pdmax
pdavg
pdmax
pdavg
vpmax
vsmax
pdmax
pdavg
vmax
icmax
ipmax
vmax
pdmax
pdavg
ismax
pdmax
pdavg
pdmax
pdavg
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Actual
Value
50
4
4
800m
800m
20
20
40
20
16
16
30
5
5
25
800m
800m
20
800m
800m
30
30
Stress Bar-chart
Value
At Ratio (%) 0%
57.3
4.07
3.78
710m
691m
16.3
15
27.7
13.7
10.5
9.2
13.7
1.68
1.68
4.17
86.4m
80.8m
1.71
28.3m
26.7m
389m
170m
7.03m
20.3m
--45.1m
--12.8m
--7.03m
7.21m
15.5m
--7.21m
42.6m
42.6m
50m
19.8m
--7.21m
16m
--32.5m
---
100%
114 XXXXXXXXXX
102 XXXXXXXXXX
94.4 --------88.7 --------86.4 --------81.3 -------75 -------69.3 ------68.3 ------65.5 ------57.5 -----45.5 ----33.5 --33.5 --16.7 -10.8 10.1 8.54 3.54 .
3.34 .
1.3 .
0.566 .
Fourier Analysis (5V Input)
1st - 2nd = 37dB separation
1st - 3rd = 50dB separation
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Transient Response (7V Input)
12.0
vload
8.0
4.0
(V)
0.0
-4.0
-8.0
-12.0
-16.0
0.0
0.01
0.02
0.03
0.04
0.05
0.06
t(s)
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0.07
0.08
0.09
0.1
Fourier Analysis (7V Input)
1st - 2nd = 26dB separation
1st - 3rd = 19dB separation
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Noise Analysis
500n
X_Max: (49169.0, 468.56n)
450n
Power Transistor q_3p.q1
400n
(1/rt(Hz))
350n
300n
250n
X_Max: (49169.0, 107.07n)
r.rsrc
200n
150n
X_Max: (49169.0, 72.188n)
r.r2
100n
50n
0.0
3000.0
6000.0
10000.0
20000.0
f(Hz)
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30000.0
60000.0
100000.0
System: Loudspeaker
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Loudspeaker
Convert electrical signals into sound
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Loudspeaker DT Analysis
0.003
diaphragm
0.002
0.001
Non-linear response. Note that the suspension
(m)
stiffness (spring_nl) is non-linear with displacement.
0.0
-0.001
-0.002
-30.0
-20.0
-10.0
0.0
10.0
20.0
/v(v.vin)(V)
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30.0
Loudspeaker Transient Analysis
(to impulse)
Oscillation due to speaker mechanical resonance
(m)
0.01
0.0
-0.01
0.0
0.04
0.08
0.12
0.16
t(s)
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0.2
0.24
0.28
Loudspeaker AC and FFT
diaphragm
-40.0
dB(m)
-60.0
-80.0
-100.0
-120.0
-40.0
-80.0
diaphragm
-140.0
dB(pos_m/Hz)
AC Analysis of Non-linear System: No Non-linear Effects Shown
0.1
0.3
1.0
3.0
10.0
30.0
100.0 300.0
f(Hz)
FFT of Ttransient Analysis: Shows Non-linear Effects
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1000.0
Linearized Spkr. Responses
dB(pos_m/Hz)
Linearized Analysis (spring_nl, winddrag=0)
-40.0
-80.0
diaphragm
-120.0
0.1
0.3
1.0
3.0
10.0 30.0
1000.0 f(Hz)
100.0
(m)
FFT Analysis with Linearized System
0.04
0.04
0.02
0.02
0.0
0.0
-0.02
-0.02
-0.04
-0.04
diaphragm
diaphragm
0.0 0.02
0.06
0.1
0.14
0.18
t(s)
IFFT of linearized Freq. Response, and original AC Analysis
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Full Audio System
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Spkr. Diaphragm Response (system)
Loudspeaker Response to DSP Filter
2.0
Audio Test Pulse
1.0
0.0
-1.0
-2.0
0.002
Unfiltered Diaphragm Response
0.001
0.0
-0.001
-0.002
0.002
DSP-filtered Diaphragm Response
0.001
0.0
-0.001
-0.002
0.0
0.02
0.04
0.06
0.08
0.1
t(s)
0.12
0.14
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0.16
0.18
0.2
Saber Analysis
Circuit Analysis with
SaberDesigner
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DC Analysis
DC (Operating Point) Analysis
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Operating Point (DC) Analysis
General Description
• The DC operating point analysis calculates the state of the system at time=0.
• This is used as an initial point for subsequent analysis.
Required Parameters
• None. You can simply select OK to run a DC operating point analysis.
Other Features/Comments
• Input and output files can be specified.
• Different algorithms are available for difficult circuits.
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Operating Point Analysis (cont.)
An operating point is a set of values that define the
steady state of a nonlinear system at time=0, with all
time-varying parameters and their derivatives set to 0.
In essence, for an operating point analysis:
All dynamic elements are effectively removed from the
circuit
• inductors are shorted
• capacitors are opened
• time-dependent sources are removed
Noise sources set to 0
AC sources set to 0
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Operating Point - Initial Point File
The results of an operating point analysis are stored in
the initial point file (typically called design_name.i2.dc).
This file serves two purposes:
It contains the operating point used in other Saber
analyses
• Saber uses it as the first data point for time-domain analysis.
• For small signal frequency analysis, Saber applies a small sinusoidal
signal around the operating point.
It provides a quick check to determine possible incorrect
part parameters
• Gives the user an idea if components have correct values, etc.
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Preparation for Lab #1
SaberSketch and SaberGuide
Work Surface Introduction
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SaberSketch/Guide Introduction
Pulldown Menu Bar
SaberGuide Icon Bar
SaberSketch Icon Bar
Schematic Window or
Symbol Window
Tool Bar
Help field
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Lab #1 - Operating Point
In this lab exercise, you will perform an operating point
analysis on the RLC circuit discussed earlier.
Perform the steps beginning on the page titled
Lab #1 in your exercise manual.
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Lab #1 Review
With vin = 0 at time = 0, all circuit nodes are 0 for DC
analysis
With vin = 1 at time = 0, vout = 0.909V
Component values can be dynamically altered in Saber
from Sketch
DC analysis results can be back-annotated to the
schematic
References: SaberBook; Analyzing Designs Using
SaberDesigner
• Inductor is shorted for DC analysis
• Capacitor is opened for DC analysis
• Vout is the input voltage across a simple voltage divider 1V*(1k/1.1k)
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Operating Point - Simulation Files
Simulation files generated during DC analyses (default names):
• design_name.dc.i1 - ASCII control file for dc.i2
• design_name.dc.i2 - Binary data file that holds results of DC analysis
• To display: di dc
• design_name.dc_err.i1 - ASCII control file for dc_err.i2
• design_name.dc_err.i2 - Binary data file used to hold initial point error
information
• design_name.dcerr.i1 - Binary data file created when DC analysis fails
to find acceptable solution. Used to store initial point information up to
the point where DC analysis failed.
• To display: di dcerr
The Saber config command can be used to generate these files in other
formats. For example: design_name.i1.dc and design_dir/dc.i1
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AC Analysis
Small Signal (AC) Analysis
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Small Signal AC Analysis
General Description
• Frequency (or small-signal AC) analysis calculates the behavior of a system as
•
a function of frequency.
This is a linear analysis about a specified operating point. The default operating
point is the output of the DC analysis.
Required Parameters
• Start Frequency - specifies the beginning frequency for the analysis.
• End Frequency - specifies the end frequency of the analysis.
Other Features/Comments
• Plot files can be user-specified to allow for file comparison.
• Operating point can be specified by the user.
• User can specify number of frequency points calculated, as well as linear or
•
logarithmic spacing of those points.
Must have an AC voltage or current source specified in the circuit.
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Why AC Analysis?
AC analyses are useful in several areas, including:
Filter design
Open and closed loop control design
Pole/Zero analysis
In general, any time you need to know how something
behaves as a function of frequency
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Small Signal AC Analysis
Small-signal AC analyses characterize non-linear systems in the
frequency domain by frequency-sweeping a small sinusoidal signal at
the input.
This small sinusoid keeps the system running in the linear region of
operation around a previously calculated operating point.
Typical AC analysis signals are shown on the following slide. The
slide shows a system’s gain (magnitude) and phase as a function of
frequency.
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Small Signal AC - Bode Example
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Small Signal AC - PZ Example
Graph0
Im(rad/sec)
20000.0
poles
c.c1=300n
15000.0
c.c1=400n
c.c1=100n
c.c1=500n
c.c1=600n
10000.0
c.c1=700n
5000.0
Im(rad/sec)
c.c1=800n
c.c1=900n
0.0
c.c1=1u
-5000.0
c.c1=200n
-10000.0
-15000.0
-7000.0
-6500.0
-6000.0
-5500.0
-5000.0
-4500.0
Re(rad/sec)
-4000.0
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-3500.0
-3000.0
-2500.0
: Re(rad/sec)
Frequency Domain Measures
Lowpass (3dB point)
Highpass (3dB point)
Bandpass (Q, ripple, etc.)
Stopband
Phase Margin
Gain Margin
Slope
Magnitude
Phase
Real
Imaginary
Nyquist Plot Frequency
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SaberScope Introduction
Pulldown Menu Bar
SaberScope Icon Bar
Graph Window
Tool Bar
Help field
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Lab #2 - Small Signal AC
In this lab exercise, you will perform frequency domain
(small-signal AC) analysis on the RLC circuit.
You will first perform a standard transfer function
analysis (and display it in Bode form), followed by a
pole/zero analysis.
Perform the steps beginning on the page titled
Lab #2 in your exercise manual.
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Lab #2 Review
Small-signal AC Analysis is linear about an operating
point
Useful whenever you want to understand something as a
function of frequency
Plot files (which contain simulation signals) are managed
with the Signal Manager; Signals are managed with the
Plot File Window
Measurements specifically designed for AC analysis can
be found using the Measurement Tool under Frequency
Domain
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Lab #2 Review - Continued
Pole/Zero analysis helps to visualize system behavior
Vary loops can be used to sweep various component
values
Vary loops can be nested
Batch measurements are possible (measurements on
multi-membered waveforms)
References: SaberBook; Analyzing Designs Using
SaberDesigner
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AC Analysis - Simulation Files
Simulation files generated during AC analyses
(default names):
• design_name.ac.d1 - ASCII control file for ac.d2
• design_name.ac.d2 - Binary data file: frequency domain data
• design_name.ac.ai_pl - ASCII control file for ac.p2
• design_name.ac.p2 - Binary plot file: extracted frequency domain data
• design_name.pz.ai_pl - ASCII control file for pz.p2
• design_name.pz.p2 - Binary plot file: extracted pole/zero data
The Saber config command can be used to generate these files in other
formats. For example: design_name.d1.ac and design_dir/ac.d1
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Transient Analysis
Time-Domain (Transient) Analysis
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Time Domain (Transient) Analysis
General Description
• Transient analysis calculates the behavior of a system as a function of time.
• Each calculated data point in time is called a time step.
Required Parameters
• End Time - specifies the end time of the analysis.
• Time Step - specifies the initial time step of the analysis.
Other Features/Comments
• Plot file names can be user-specified to allow for file comparison.
• Sample Point Density and Max Truncation Error can be adjusted to
•
calibrate accuracy.
Transient analyses can start from zero (no Operating Point analysis required);
they can also be restarted (continued from previous end point).
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Time Domain - Example
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Setting the Time Step Field
Saber uses the value in the Time Step field to determine
an initial guess at the next solution point in the
simulation.
Typically, set this to 1/100th or 1/1000th of tend
Rule of thumb otherwise,
Set this value to the smallest of:
1/10th of the smallest relevant time constant in the design
Shortest rise of fall time of a square/pulse wave driving source
1/100th of the input period of a sinusoidal driving source
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Time Domain Measures
Falltime
Risetime
Slew Rate
Period
Frequency
Duty Cycle
Pulse Width
Delay
Overshoot
Undershoot
Settle Time
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Lab #3 - Time Domain
In this lab exercise, you will perform a time domain
(transient) analysis on the RLC circuit.
Perform the steps beginning on the page titled
Lab #3 in your exercise manual.
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Lab #3 Review
Time-Domain analyses are characterized by having time
as the independent axis (X-axis)
The results appear similar to how the would look on an
oscilloscope
Graph signals are plotted in graph regions in
SaberScope. Users can select which region is used.
Measurements specifically designed for Transient
analysis can be found using the Measurement Tool
under Time Domain
References: SaberBook; Analyzing Designs Using
SaberDesigner
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TR Analysis - Simulation Files
Simulation files generated during transient analyses
(default names):
• design_name.tr.i1 - ASCII control file for tr.i2
• design_name.tr.i2 - Binary data file that holds the final results of the
transient analysis (end point)
• To display end point: di tr
• design_name.tr.d1 - ASCII control file for tr.d2 and tr.d3
• design_name.tr.d2 - Binary data file: time domain data
• design_name.tr.d3 - Binary data file: event-driven analog and digital
simulation data (if applic.)
• design_name.tr.ai_pl - ASCII control file for tr.p2 and tr.p3
• design_name.tr.p2 - Binary plot file: extracted analog time domain data
• design_name.tr.p3 - Binary plot file: extracted event-driven analog and
digital time domain data
You may optionally change the names of, or suppress most of these
files depending on user-specified Saber settings.
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Sensitivity Analysis
Sensitivity Analysis
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Sensitivity Analysis
General Description
• Used to determine how sensitive a specified design performance measurement
•
is to variations in design parameters
A performance measurement is a single numeric characteristic of the circuit
(e.g. DC voltage, risetime, bandwidth, etc...)
Required Parameters
• Parameter List - specifies the design parameters to be varied (perturbed)
• Add Analyses/Measures - specifies which analyses/measures to use after
each perturbation
Other Features/Comments
• Saber changes each design parameter by a small amount and calculates the
•
•
effect on the performance measure
Sensitivity Analysis is small-signal (assumes linearity)
Tolerance data not used
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Sensitivity Calculations
Sensitivity calculations:
m m
sensitivity
p p
( m) / (m) p m
normalized _ sensitivity
( p) / ( p) m p
where p is the parameter value and m is the performance
measure
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Why Sensitivity Analysis?
In the previous example, you performed a time domain
analysis and measured the voltage overshoot as a result
of the filter.
Now, you can use sensitivity analysis to determine which
component(s) are contributing the most to this unwanted
overshoot.
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Lab #4 - Sensitivity Analysis
In this lab exercise, you will perform a sensitivity analysis
on the RLC circuit.
Perform the steps beginning on the page titled
Lab #4 in your exercise manual.
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Lab #4 - Review
Sensitivity Analysis helps isolate component’s
contribution to a given performance measure
This is a small-signal analysis, linearized about an
operating point
References: SaberBook; Analyzing Designs Using
SaberDesigner
Analog and Digital Filters: Design and Realization
by Harry Y-F. Lam, Prentice-Hall, ISBN 0-13-032755-7
Chapter 9 (page 321-337) [contains further references]
Analog Filter Design
by M. E. Van Valkenburg, Holt, Rinehart, and Winston, ISBN 0-03-059246-1
See Chapter 9 (page 261 through 278) for Sensitivity
Analysis and Design of Analog Integrated Circuits
By Paul R. Gray and Robert G. Meyer, John Wiley & Sons, ISBN 0471-87493-0
See Chapter 11 (page 635-702) for Noise
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Lab #4 Review cont.
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Sensitivity Analysis - Simulation Files
Simulation files generated during sensitivity analyses
(default names):
• all analyses specified in the sensitivity analysis form
• design_name.cleanup.wf - Saber control file - ASCII
• design_name.loop.wf - Saber control file - ASCII
• design_name.sens.r1 - Intermediate analysis report file
• sens.rpt - Sensitivity analysis report file (optional)
You may optionally change the names of, or suppress most of these
files depending on user-specified Saber settings.
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MC Analysis
Monte Carlo (Statistical) Analysis
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Monte Carlo (statistical) Analysis
General Description
• Monte Carlo analysis randomly varies component parameters, within userspecified tolerance ranges, and executes the specified Saber analysis at each set
parameter values.
Required Parameters
• Runs - specifies the number of Monte Carlo “loops”
• Add Analyses/Measures - specifies which analyses/measures to use after
each perturbation
Other Features/Comments
• Saber changes each component value every time the loop is executed
• Large or small-signal analyses allowed (can be non-linear)
• Tolerance data is used
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Monte Carlo
MC Analysis results are often represented as scatter
plots
Scatter plots are useful for spotting trend or correlation
between a given measure and a component parameter
Data can also be represented in histogram format
Circuit mins, max’s, std dev, etc. are also available
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Scatter Plot Measurements
Scatter Plots can also be used to view parameter values used
during the Monte Carlo Analysis
Scatter Plots can also be easily converted into histograms to view
distributions
Scatter Plot and Corresponding Histogram for Bias Resistor
() : _run(-)
12000.0
rnom(r.pbias)
10000.0
Plotted directly from
parameter plot file
8000.0
0.0
25.0 50.0
75.0 100.0 0.125k 0.15k 0.175k 0.2k 0.225k 0.25k 0.275k 0.3k
_run(-)
(1) : rnom(r.pbias)()
40.0
Mean: 10022.0
count
Created using Statistical->Histogram
in the Measurement Tool
20.0
std_dev: 334.25
0.0
8.5k
9.0k
9.5k
10.0k
rnom(r.pbias)()
10.5k
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11.0k
Correlation Plots
Provide information on interactions between technologies
Statistical correlation plots convert simulation data into design
information
Min Sensor Voltage vs. Damping (good correlation)
0.9
Min Sensor Voltage vs. Bias Resistor (no correlation)
(V) : d(damper_t.visc)()
LocMin(sens_point)
0.9
0.85
0.85
0.8
0.8
0.75
0.75
0.7
0.7
0.65
0.65
0.6
0.6
5.0
6.0
7.0
8.0
9.0
10.0 11.0 12.0 13.0 14.0 15.0
8.5k
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LocMin(sens_point)
9.0k
9.5k
10.0k
rnom(r.pbias)()
d(damper_t.visc)()
(V) : rnom(r.pbias)()
10.5k
11.0k
Lab #5 - Monte Carlo Analysis
In this lab exercise, you will perform a Monte Carlo
analysis on the RLC circuit.
Perform the steps beginning on the page titled
Lab #5 in your exercise manual.
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Lab #5 - Review
What’s the difference between Sensitivity and MC
analyses?
• MC analysis allows all component values to be simultaneously set to
•
random values within each component’s specified tolerance band.
Sensitivity analysis causes each component, one at a time, to be
changed by a very small amount, while the results of that change with
respect to some measurement are recorded.
References: SaberBook; Analyzing Designs Using
SaberDesigner; Advanced Saber/MAST Class
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Monte Carlo Analysis
Simulation Files
Simulation files generated during MC analyses
(default names):
• all analyses specified in the MC analysis form
• design_name.body.wf - file that holds simulation commands - ASCII
• design_name.cleanup.wf - Saber control file - ASCII
• design_name.loop.wf - file holds the loop transcripts - ASCII
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Automating SaberDesigner
Automating SaberDesigner
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Automating SaberDesigner
SaberDesigner has three very powerful automation features:
Saber Command Scripts
Macro Recorder
AIM Scripts
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Saber Command Scripts
All of the Saber commands you have run via the menus can also be run
from the command line.
For example, to alter resistor r.r1 from its current value to 2k ohms, you
could type: alter r.r1=2k. (or simply, a r.r1=2k).
In fact, everything you executed through the menu interface was translated
into these commands.
These are the commands that appear in the SaberGuide Transcript window
as they’re executed. The commands are also written to a file called
design.out.
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Saber Command Scripts
For example, in the last lab, you executed the
following analyses:
Run a DC Analysis
Run a Transient Analysis, view vout
•
•
•
•
•
End Time: 10m
Time Step: 10n
Monitor Progress: 100
Plot After Analysis: Yes - Open Only
Max Truncation Error: 100u
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Saber Command Scripts
However, you could have just as well typed the following directly into the
SaberGuide Transcript window’s command line:
dc
tr (te 10m, ts 10n, mon 100, terr 100u)
pl
or alternately,
dc; tr (te 10m, ts 10n, mon 100, terr 100u); pl
•
•
•
•
•
•
where dc means DC Analysis
tr means TRansient Analysis
te means the End Time
ts means the Time Step
terr means the Max Truncation Error
mon means the Monitor Progress (some of which are in parenthesis, implying that they
apply to the transient analysis)
• pl means Plot After Analysis
• The semi-colons act as carraige returns
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Saber Command Scripts
Saber commands can also be entered into a file, and then the
file itself can be executed from the Saber command line. Such
files are called Saber Command Scripts. The extensions to
these files should be .scs.
Advantages:
• save the user from entering repetitive commands
• provide the user with a transcript for documentation purposes and
analysis repeatability
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Macro Recorder
Automatically makes a record of the actions performed by a
user in a given Saber session.
Allows simulation and post-processing steps to be repeated
without the user having to type all of the commands into a file
by hand
Stores all recorded information in a user-editable format
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Macro Recorder Window
Icon Bar
Edit Macro
Delete Macro
Close Macro
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Macro Recorder Icon bar
Pause Macro
Record Macro
Play Macro
End Macro
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Browse
AIM Scripting Language
The AIM (Analogy Inc. Macro) scripting language is a powerful part of the
Saber toolset
Based on the Tcl/Tk language from UC Berkeley
Interpreted language that does not require compilation
The entire SaberDesigner interface is written in AIM
Can be used to easily create custom Graphical User Interfaces (GUI’s) to
perform specific tasks
Macros can be recorded and replayed to increase productivity by
automating repetitive tasks
Many useful AIM scripts available in the User Group Library
($SABER_HOME/user_grp/AimMacro directory)
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Pareto Analysis Script
These histograms can be created for any measurement
LocMin(sens_point)
rnom(r.sens)
1.0
(-) : par(-)
Sensitivity
Sensitivity
0.5
Sensitivity Histograms indicate
magnitude and direction of
least-squared fit line though
correlation scatter plots
d(damper_t.visc) k(spring_t.preld)
0.0
r(el_magnt.emag)
lmax(el_magnt.emag)
-0.5
(-) : par(-)
0.8
R**2
d(damper_t.visc)
0.6
0.4
rnom(r.sens)
0.2
lmax(el_magnt.emag)
r(el_magnt.emag)
k(spring_t.preld)
0.0
0.0
0.5
1.0
1.5
2.0
2.5
par(-)
3.0
3.5
4.0
4.5
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5.0
R-Squared Correlation histograms
indicate the “tightness” of the
scatter points around the leastsquared fit line.
Pareto Scatter Plots
The Pareto macro creates a scatter plot for each parameter appearing in the
Parameter field
Provides information on interactions between technologies
LocMin(sens_point) vs d(damper_t.visc)
(V) : d(damper_t.visc)()
0.9
LocMin(sens_point)
R**2 = 0.6366
LocMin(sens_point) vs lmax(el_magnt.emag)
(V) : lmax(el_magnt.emag)()
0.9
R**2 = 0.04159
LocMin(sens_point)
0.8
0.8
0.7
0.7
0.6
0.6
4.0
6.0
8.0
10.0
12.0
d(damper_t.visc)()
LocMin(sens_point)
14.0
0.05
16.0
Least-Squares
fit lines generated
automatically by
Pareto macro
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0.055
0.06
0.065
lmax(el_magnt.emag)()
LocMin(sens_point)
0.07
Lab #6 - Automating SaberDesigner
In this lab exercise, you automate analyses you
previously performed on the RLC circuit.
Perform the steps beginning on the page titled
Lab #6 in your exercise manual.
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Automating SaberDesigner Review
You can dynamically issue commands to Saber using
the command line directly, or by using Saber Command
Scripts
Actions you take in Saber/Sketch/Scope can be
automatically recorded and replayed using the Macro
Recorder
Virtually unlimited control of Saber is possible using the
Analogy Incorporated Macro (AIM) language
References: SaberBook - AIM Tutorial; Tcl and the Tk
Toolkit (Ousterhout); Practical Programming in Tcl and
Tk (Welch)
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MC Script (pre-edited)
Saber:Send {mc (parfile pars_mc,parlist rnom(r.r1) rnom(r.r2) c(c.c1) l(l.l1),runs 10,seed constant}
Saber:Send {tr (monitor 100,tend 5m,terror 100u,tstep 10n}
Saber:Send {end}
Saber:Send {pl}
ScopeSigMgr:loadpffile C:/scott/Training/bd_lvl_5.0/labs_tst/RLC/ex_rlc_mc.tr 1 openonly
Graph addsignal WF:1:6 -region new -tracehi 2
GrMeas:Overshoot Graph0 Signal0 default xyrangeAll Meas0vsP - activeGraph
Graph:Select Graph0
Graph:DSel
Graph itemselect Signal1 add
GrMeas:Levels Graph0 Signal1 Maximum xyrangeAll
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MC Script (post-edited)
Saber:Send {mc (parfile pars_mc,parlist rnom(r.r1) rnom(r.r2) c(c.c1) l(l.l1),runs 10,seed constant}
Saber:Send {tr (monitor 100,tend 5m,terror 100u,tstep 10n}
Saber:Send {end}
Saber:Send {pl}
set pf [ScopeSigMgr:loadpffile C:/scott/Training/bd_lvl_5.0/labs_tst/RLC/ex_rlc_mc.tr 1 openonly]
set wf [pf:read $pf vout]
Graph addsignal $wf -region new -tracehi 2
GrMeas:Overshoot $Graph(graph) Signal0 default xyrangeAll Meas0vsP
GrMeas:Levels $Graph(graph) Signal1 Maximum xyrangeAll
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Stress Analysis
Stress Analysis
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Stress Analysis
General Description
• Used to determine the stress levels of the devices in a system
• A device is overstressed if it is being used outside its intended region of
operation.
Required Parameters
• Independent Source name (e.g. v_dc.v1).
• Sweep Range
Other Features/Comments
• Requires DC Operating Point analysis to be run first
•
(or run from zero)
Input and output files can be specified.
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Stress Analysis
Used to determine the stress levels of the devices in a system
A device is overstressed if it is being used outside its intended region of
operation
A quantity called "Stress Ratio" is used to determine the stress level for each
device as shown below:
If the Stress Ratio exceeds "1" then the device is considered to be overstressed
Thermal effects can also be included (see Engineering Note 110)
Stress_ Ratio
Measured _ Value
( De) Rated _ Value
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Stress Measures
A stress measure is a definition of an operating condition
for which a rating (operating limit) can be specified. For
example:
• Power dissipation in a resistor
• Reverse voltage across a capacitor
• Junction temperature of a bipolar transistor
Power
PDmax
0
Tc
Tjmax
Ambient
The area under the curve shown above is referred to as the “Safe Operating Area”
(SOA). The SOA defines the region in which the component can operate without stress.
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Stress Measures - with derating
Power
PD max
50% derating curve
50%PDmax
0
Tc
Tj max
Ambient
Temperature
When the SOA is derated, the component has a smaller range from which to safely
operate.
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Stress Ratings
Maximum rated value is typically derated by multiplying it by a
derating factor (e.g. 0.5 for 50% derating)
Derating File Examples:
/instance_path
part_type
part_class id derating_value
/...
/r.*
/.../q2n3055.*
*
resistor
*
*
*
*
*
*
*
0.9
0.5
0.8
Analogy Components have built-in ratings, otherwise the information
must be manually added by the user.
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Stress Circuit - Power Amplifier
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Saber Include File
Allows user to define global simulation arguments
Allows user to specify “include” files for netlist
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Lab #7 - Stress Analysis
In this lab exercise, you will perform a Stress Analysis on
the power amplifier.
Perform the steps beginning on the page titled
Lab #7 in your exercise manual.
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Stress Analysis Report
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Stress Analysis Report
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Lab #7 Review
Stress Analysis checks for circuit operation within SOA of
components in design
The information required for Stress Analysis is already
incorporated in Component Library models
Users can incorporate their own stress information for
models
Manufacturer SOA levels can be changed using derating
files
References: SaberBook; Analyzing Designs Using
SaberDesigner; Advanced Saber/MAST Class
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Stress Analysis - Simulation Files
Simulation files generated during Stress analysis
(default names):
•
•
•
•
design_name._stress.ai_pl - ASCII control file for _stress.p2
design_name._stress.p2 - Binary data file: extracted stress data
design_name.stress.r1 - Intermediate analysis report file
stress.rpt - Stress Report (optional)
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Fourier Analysis
Fourier Analysis
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Fourier Analysis
General Description
• Transforms periodic time-domain waveforms into a frequency spectrum
• Produces a line spectrum showing the spectral content at the DC value, fundamental
frequency, and specified number of harmonics
Required Parameters
• None
Other Features/Comments
• Requires transient analysis to be run first
• Input and output filenames can be specified
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Fourier’s Theorem
According to Fourier’s theorem, any periodic waveform can be represented by
the sum of its average and a series of sine waves.
The sine waves have frequencies of integer multiples of the frequency of the
periodic function, and varying magnitudes and phases.
f(t) = a0 + a1 cos w0t + a2 cos 2w0t + … + b1 sin w0t + b2 sin 2w0t …
The discrete Fourier transform allows the magnitudes and phases of the sine
waves to be determined from data points along a period of the function.
The range of the data points is from the end of the analysis to one period before
the end of the analysis.
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Fourier Analysis
The main advantage of doing this is to allow easy
discrimination between large and small sinusoids in a given
waveform
For example, you want to test the purity of an oscillator:
• Time Domain: the ripple you want to measure may be buried in the larger
•
signal it’s super-imposed upon.
Frequency Domain: all signals of varying frequency are represented on their
own spot on the frequency axis, distinct and separate from the other signals.
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Fourier Analysis - Example
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Lab #8 - Fourier Analysis
In this lab exercise, you will perform a Fourier Analysis.
Perform the steps beginning on the page titled
Lab #8 in your exercise manual.
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Lab #8 Review
Was there a difference between the 5V input and 8V
input simulations? Why?
Fourier analysis is really just another way of
representing existing data
References: SaberBook; Analyzing Designs Using
SaberDesigner
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Fourier - Simulation Files
Simulation files generated during Fourier analyses
(default names):
• design_name.fou.ai_pl - ASCII control file for fou.p2
• design_name.fou.p2 - Extracted binary plot file
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DC XFER Analysis
DC Transfer Analysis
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DC Transfer Analysis
General Description
Sweeps an independent DC voltage or current source over a user-defined range of value
and computes the DC operating point for each sweep value.
Required Parameters
• Independent Source name (e.g. v_dc.v1).
• Sweep Range
Other Features/Comments
• Requires DC Operating Point analysis to be run first (or run from zero)
• Input and output files can be specified.
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DC Transfer - Example
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DC Xfer - Loudspeaker Circuit
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Lab #9 - DC Transfer Analysis
In this lab exercise, you will perform a DC Transfer
Analysis.
Perform the steps beginning on the page titled
Lab #9 in your exercise manual.
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Lab #9 Review
DC Transfer analysis allows you to study a circuit with
the x-axis (independent variable) chosen as something
other than time. (Great for transfer function analysis)
This analysis can also be performed using nested VARY
loops
References: SaberBook; Analyzing Designs Using
SaberDesigner
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DC Transfer - Simulation Files
Simulation files generated during DC Transfer analysis
(default names):
• design_name.dt.i1 - ASCII control file for dt.i2
• design_name.dt.i2 - Binary data file that holds the end point results of
the DT analysis
• To display end point: di dt
• design_name.dt.d1 - ASCII control file for dt.d2 and dt.d3
• design_name.dt.d2 - Binary data file: analog simulation data
• design_name.dt.d3 - Binary data file: event-driven analog and digital
simulation data (if applic.)
• design_name.dt.ai_pl - ASCII control file for dt.p2 and dt.p3
• design_name.dt.p2 - Binary plot file: extracted analog data
• design_name.dt.p3 - Binary plot file: extracted event-driven analog
and digital time domain data
You may optionally change the names of, or suppress most of these
files depending on user-specified Saber settings.
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Mixed-Signal Analysis
Mixed-Signal Analysis
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Mixed-Signal Analysis
General Description
Capability to simulate designs that contain both analog and digital components.
Required Parameters
• None. This process is typically transparent to the user (particularly for native
simulations).
Other Features/Comments
• Works with or without Partner digital simulators
• Allows users to specify various hypermodels
• This capability makes Z-domain and general state-driven simulation possible
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Mixed-Signal Analysis
The Calaveras Algorithm synchronizes the analog and digital simulators
within the Saber simulator
Optimizes both accuracy and speed
Hypermodels handle signal flow between analog and digital systems
Include non-linear loading, driving, and rise and fall time
Mixed-mode may be run “native” (Saber digital), and
• Saber/ModelSim (Mentor Graphics)
• Saber/Verilog-XL (Cadence)
• Saber/Fusion (Viewlogic)
Mixed-simulator products can be run from either the Saber Menu Interface
or the digital simulator’s interface
A model may exist in both analog and digital systems
• e.g. lm555, op2, comp_l4, pwm_l4, r2r_16
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Hypermodels
An interface is created between models that have analog (electrical)
and digital (using logic_4 states) connections. This is done by
inserting a Hypermodel interface template between these two
different types of connection points.
For example, a Hypermodel template would be required between a
discrete transistor driving a NAND gate or between a four-bit
counter driving a resistor ladder.
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Analog/Digital Boundary - Hypermodels
d2a
P
P
P
P
N
N
N
N
a2d
3500 parts already characterized by Analogy
Models for TTL, ECL, CMOS, ideal behavioral, ...
Hypermodels® inserted automatically by the Frameway
Templates to customize to specific requirements
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Hypermodels
Netlisters used with the Saber simulator will automatically insert
appropriate Hypermodel templates wherever needed.
Simply stated, the main function of a Hypermodel interface template is to
provide state mapping between two simulators—one of which uses analog
models, the other of which uses digital models.
• A Hypermodel interface template does NOT determine
•
VALUES WITHIN an analog or digital model (such as propagation delay
within a digital part).
A Hypermodel interface template is used ONLY to convert
VALUES AT A DIGITAL PIN.
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Hypermodel I/O
Hypermodel templates emulate input and output terminal
characteristics
• Include the loading effects of a given digital technology.
A Hypermodel template can be considered as a single-bit,
digital-to-analog or analog-to-digital converter that models the
following:
• Transition characteristics
• Terminal (loading) characteristics
Transition characteristics (such as rise and fall times) of all Hypermodel
templates are similar. However, terminal characteristics vary according to
the technology of the digital circuit being modeled.
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Hypermodel Logic Levels
Analogy Hypermodel templates recognize only the following logic levels:
0, 1, X, Z. These logic levels are represented by digital states that use
logic_4 values shown below.
These values are defined in the units.sin file that is automatically loaded
when running the Saber simulator.
l4_0
0 (LOW)
l4_1
1 (HIGH)
l4_x X (uncertain—not treated as “don’t care”)
l4_z
Z (high impedance)
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Generic Hypermodel Templates
Technologies of Hypermodel Templates
The Standard Template Library provides generic Hypermodel templates for
analog-to-digital (a2d), digital-to-analog (d2a), and bidirectional (bi)
conversion of the following digital technologies:
•
•
•
•
ideal (four transition parameters, four terminal parameters)
CMOS (complementary MOSFET)
ECL (emitter-coupled logic)
TTL (transistor-transistor logic)
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Hypermodel Templates (Std. Lib)
The information that defines the particular Hypermodel “type” is located in
“technology” files. Several examples of these technology files are given below:
Ideal
ECL
CMOS
TTL
ide_tech ecl_tech mos_tech
ttl_tech dd_a2d
ide_a2d ecl_a2d mos_a2d
ttl_a2d
ide_a2dn ecl_a2dn mos_a2dn
ttl_a2dn dd_d2a
ide_bi
mos_bi
ttl_bi
mos_bin
ttl_bin
ide_d2a ecl_d2a mos_d2a
ttl_d2a
ide_d2an ecl_d2an mos_d2an
ttl_d2an
ecl_bi
ide_bin ecl_bin
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Digital-to-digital
dd_bi
Hypermodel (Native and Partner)
Native Hypermodel templates (whose names end in “n”)
are used when the Saber simulator serves as both the
digital and analog simulator
Mixed-simulator Hypermodel templates are used when
Saber is the analog simulator and is partnered with a
digital simulator
The only difference between these types of templates is
their declaration of connection points—the models they
provide are identical (e.g., the models provided by
mos_a2d and mos_a2dn are identical).
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Calaveras Algorithm
Synchronizing Analog and Digital
141
# 141
7/17/2015
Calaveras: Features & Benefits
Achieve optimal performance speed using patented
Calaveras algorithm
• Faster simulations
• More accurate simulations
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Boundary Algorithms
• Analog time step at
every digital event
Digital
• Very slow!
Analog
• Synchronize at
periodic rate
• More analog error
is incurred
• Reevaluate at
backtrack
• Bad for highly
fedback systems
Lock-step
Fixed Time-step
Digital
Analog
Ping Pong
Digital
Analog
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Simulating with Calaveras
Digital
Events
Analog
time steps
Roll-back
No lost digital events and no lost time resolution. Most accurate
results
Unlimited feedback between analog and digital simulators for
complex circuitry
Calaveras is the fastest, most accurate algorithm
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Simulating with Calaveras
A
A
B
C
5
D
9
7
B
10
11
gate input
threshold
4
3
2
1
C
D
6
8
Number indicates sequence of simulation time points
No analog time step at digital step “6”
Analog time step “7” is ignored and Calaveras rolls-back to analog time step
“9”
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Simulating with Calaveras
S A to D Converter
716
Source: NEC Corporation, 1997
50
CPU time Normalized
Timesteps Normalized
26
1
Saber
1
“A”
“B”
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1 1
FORTRAN
Preparation for Lab #10
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Lab #10 - Mixed-Signal Simulation
In this lab, you will perform mixed-signal simulation on a
counter circuit. You will netlist the circuit with various
hypermodels and observe simulation results of each.
Perform the steps beginning on the page titled
Lab #10 in your exercise manual.
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Lab #10 Review
Hypermodels are automatically inserted at the boundary
between analog and digital pins.
• Hypermodels do not exist at the schematic level: they are inserted
during netlist generation.
• The inserted hypermodels can be viewed by looking directly at the
netlist.
• Users can specify the hypermodel technology that is used.
References: SaberBook; Analyzing Designs with
Saber/ModelSim; Getting Started with Saber/ModelSim;
Introduction to MAST Class; Advanced Saber/MAST
Class
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Netlists
Netlists
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Why Should You Understand Netlists?
In the labs you have just completed, the instructions you were given should have
allowed you to progress through without many difficulties. But what do you do
when you DO encounter a problem?
Often, the best way to identify schematic entry or syntax problems in your design is
to go to the netlist. There are some good reasons to do this:
• Often, Saber will give you a warning or error message that directly references the line
•
•
•
•
number in a netlist.
The netlist is what is actually read in and used by saber. It is your direct link to Saber
(whereas the schematic is only there to help generate a netlist).
Sometimes you will want to see the actual template argument syntax as it appears in
the netlist, rather than the way you may add it at the schematic level (these are often
different to simplify schematic entry).
Certain changes can be made faster at the netlist level than at the schematic level.
You do not need SaberSketch or any other front-end schematic package to run Saber
once you have a netlist.
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Netlists
inductor.l1
resistor.r1
in p
m
x
p
m
1m
p
capacitor.c1
out
1k
m
1u
Cons ta nt s don’t h ave un it s in S a ber
Squares represent component pins (p and m are pin names), and dots represent
connection points—circuit nodes (in, out, x are net names). The netlist, or
description of this symbolic circuit representation would be:
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Netlists
inductor.l1
resistor.r1
in p
m
x
p
m
1m
p
capacitor.c1
1k
m
1u
Cons ta nt s don’t h ave un it s in S a ber
in ductor.l1 p:in m:x = l = 1m
r es ist or.r 1 p:x m :ou t = r n om = 1k
ca pa cit or.c1 p:in m :ou t = c = 1u
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out
Prefix Abbreviations
a
atto
10-18
f
p
n
u (or mu)micro
m
k
meg (or me)
g
t
femto
pico
nano
10-6
milli
kilo
mega
giga
tera
10-15
10-12
10-9
10-3
103
106
109
1012
You can express a number as a constant immediately followed by an appropriate
abbreviation (do not include units).
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Prefix Abbreviations - Examples
For example, the following are equivalent:
x = 3p x = 3e-12
The following are illegal specifications for numbers:
x = 3 p (space not allowed between number and abbreviation)
x = 1mA (units not allowed)
155
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Netlists - Pin Connections
Example:
r.load out 0 = 47
template_name is the name of the template.
instance_name (also known as refdes (reference designator)) is an identifier
which for this template is unique in this netlist.
connection_point_assignments assign the template’s connection points to the
netlist’s nodes. If the connection_point_assignments are in the same order that the
connection points appear in the template header, then only the nodes need be
named. Otherwise, use explicit assignments:
connection_point_name:node_name
Example:
r.load p:out m:0 = 47
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Netlists - Argument Assignments
Arguments are assigned as a comma (,) separated list of expressions which assigns
values to the template’s arguments. Any legal MAST expression of parameters and
constants may be used. If the argument assignments are in the same order that the
arguments appear in the template header, then only the expressions need be named.
Otherwise, use explicit assignments:
argument_name = expression
Example:
r.load out 0 = rnom = 47
Example:
r.1 a b = rnom = res * sin(math_pi/3)
157
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Netlist - Example
q3
5
q4
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Netlist - Example
r.r1 m:top_base p:vcc = rnom=1k
r.r2 m:n2 p:top_base = rnom=3.3k
r.r3 m:bot_base p:n3 = rnom=3.3k
r.r4 m:vee p:bot_base = rnom=1k
r.r5 m:in_base p:vin = rnom=27k
q2n2907a.q1 b:top_base c:out e:vcc
q2n3227.q2 b:bot_base c:out e:vee
q2n3904.q3 b:in_base c:n2 e:0
q2n3906.q4 b:in_base c:n3 e:0
v.vcc m:0 p:vcc = dc=15
v.vee m:vee p:0 = dc=15
v_pulse.in m:0 p:vin = initial=5, pulse=5, width=200u, period=1m, \
tr=1u, tf=1u, ac_mag=1, ac_phase=0
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Lab #11 - Netlists
In this lab, you will create a netlist from scratch without
using SaberSketch, and then debug a netlist.
Perform the steps beginning on the page titled
Lab #11 in your exercise manual.
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Netlist Review
Netlists are the text files that Saber actually uses for
simulation
Netlists can be generated by SaberSketch (or another
front-end tool), or by hand
Certain simulation problems can be best troubleshot at
the netlist level
References: SaberBook; Introduction to MAST Class
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Other Saber Files
filename.tbl - a binary file that contains a snapshot of the current
state of the simulator. Saber uses this file when resuming a
simulation.
filename.ai_sch - schematic diagram
filename.ai_sym - model symbol
filename.ai_prj - stores SaberGuide settings (like netlisting options,
etc.)
filename.ai_dsn - contains information for simulation and hierarchy
management
filename.ai_grm - stores back-annotation and cross-probing info
filename.ai_ns - Netlist State file (mapping and hypermodel info)
*.out - netlister and Saber transcript files
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Other Saber Files
Site-wide preference files
User-specific preferences
Session-specific preferences
Startup Files
Log Files
• aim.site, guide.site, scope.site, sketch.site
• .aim_user, .guide_user, .scope_user, .sketch_user
• .guidecfg, .scopecfg, .sketchcfg
• .guideRc_user, .scopeRc_user, .sketchRc_user
• .guideRc.site, .scopeRc.site, .sketchRc.site
• guide.log, scope.log, sketch.log
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Saber Measurements
Measurements are the the key to design analysis
Over 50 built-in measurements at your fingertips
Can be applied graphically in SaberScope or in "Batch" mode
when used with Sensitivity analysis or automatic data collection
Custom measurements can be added by the user
InSpecs measurements transform simulation data into design
information
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Inspecs Measurements
Time Domain:
• duty cycle, frequency, period, pulsewidth, risetime, falltime, slew rate, delay, overshoot,
undershoot, settle time, slope
Frequency Domain:
• lowpass, highpass, bandpass (Q, ripple, etc.), stopband, phase margin, gain margin, group
delay, slope
Reference or level measurements:
• max, min, X at max, X at min, peak to peak, topline, baseline, amplitude, average, RMS, ACcoupled RMS
General Measurements:
• at X, at Y, delta X, delta Y, length, slope, local min/max, crossing, horiz. level, vert. level, point
marker
Statistics:
• Max, min, range, mean, median, std. deviation, mean (+/- 3 std dev), histogram, yield, Dpu,
Cpk
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MAST Preview (Optional Section)
Building Your Own Models
166
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Mixed-signal Hardware Description
Language
MAST is a fully functional Mixed-signal Hardware
Description Language (MSHDL)
The simulator accepts an ASCII file
The model development procedure is as follows:
Existing models can be included with the equations of a
new model (i.e. netlist entries can be put into model)
• Write your model in MAST and put file in your working directory.
Models will only run in SABER
167
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General Template Syntax and Structure
template header
unit and pin_type definitions
header declarations
{
local declarations
parameters {
parameter assignments
}
netlist statements
when {
state assignments
}
values {
value assignments
}
control_section {
simulator-dependent control statements
}
equations {
equations describing behavior
}
}
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Resistor Template (Equations)
+ vr p
Characteristic Equation:
m
ir = vr / res
res
ir
MAST Template
template resistor p m = res
electrical p, m
number res
{
equations {
i(p->m) += v(p,m)/res
}
}
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Resistor with Power (Values)
template resistor p m = res
electrical
p, m
number res
{
val p power
val i ires
values {
ires = v(p,m)/res
power = v(p,m)*ires
}
equations {
i(p->m) += ires
}
}
170
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Resistor with Temp. (Parameters)
element template r_temp p m = rnom, tc1, tc2, tnom
electrical p,m
number rnom, tc1=0, tc2=0, tnom = 27
external number temp
{
number r_tmp
parameters {
r_tmp = rnom*(1+tc1*(temp-tnom)+tc2*(temp-tnom)**2)
}
equations {
i(p->m) += v(p,m)/r_tmp
}
}
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Constant Current Source Template
p
Characteristic Equation:
m
cur = constant
cur
MAST Template
template isource p m = cur
electrical p, m
number cur
{
equations {
i(p->m) += cur
}
}
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Capacitor Template
+ vc -
Characteristic Equation:
m
p
cap
ic =
ic
d(cap*vc)
dt
MAST Template
template capacitor p m = cap
electrical p, m
number cap
{
equations {
i(p->m) += d_by_dt(cap * v(p,m))
}
}
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Inductor Template
Characteristic Equation:
+ vL p
m
vL =
ind
iL
MAST Template
template inductor p m = ind
electrical p, m
number ind
{
var i il
equations {
i(p->m) += il
il: v(p,m) = d_by_dt(ind*il)
}
}
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d(ind*iL)
dt
VCVS Template
p
Characteristic Equation:
vp
vin
VCVS
vm
vout = gain*vin
vout
Choose iout such that Kirchoff’s Voltage Law is satisfied
m
MAST Template
template vcvs vp vm p m = gain
electrical vp, vm, p, m
number gain
{
var i iout
equations {
i(p->m) += iout
iout: v(p,m) = gain*v(vp, vm)
}
}
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Digital Inverter
Truth Table
in
IN
l4_0
l4_1
l4_X
l4_Z
out
MAST Template
template inverter in out
state logic_4 in, out
{
when (event_on(in)) {
if (in == l4_0)
else if (in == l4_1)
else if (in == l4_x)
}
OUT
l4_1
l4_0
l4_X
unchanged
schedule_event(time, out, l4_1)
schedule_event(time, out, l4_0)
schedule_event(time, out, l4_x)
}
There’s no “l4_z” here since output is unchanged (don’t do anything)
176
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MAST References
SaberBook
Introduction to MAST Class
Advanced Saber/MAST Class
Modeling with An Analog Hardware Description
Language (Mantooth and Fiegenbaum; Kluwer
Academic publishers)
• Guide to Writing Templates
• MAST Reference Manual
• Model Fundamentals
177
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Saber and SPICE (Optional Section)
There are two fundamental simulation approaches
currently available.
SPICE (or SPICE-like)
Saber
178
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SPICE Features
Emphasis on electronic circuit simulation
Electrical domain but is used through duality's to model
other domains such as mechanical, thermal, hydraulic
etc. (For example: assume current is fluid flow and
voltage is pressure in hydraulic domain)
Most versions have approximately 30 models built into
the simulator. (Models here, are the mathematical
description of the part i.e. Gummel-Poon transistor
equations, the diode equation, Ohms Law etc.)
Can write functions into Spice however they can not
constrain equations relating through variables to across
variables
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SPICE Features
Has Post Processing graphics and some versions have a waveform
calculator
Can do signal flow analysis with some control system analysis
capabilities
Large electronic component library (Diodes, transistors, SCR’s,
IGBT’s, opamp’s, comparators)
Runs on PC’s (Windows 3.1, 95 & NT) and Unix workstations
Analysis types: AC, DC, transient, FFT, IFFT, Monte Carlo, Noise,
Sensitivity
Some versions can link in C and FORTRAN routines
Mixed Signal in some versions (Not true digital event scheduler with
coordination Algorithm with analogy engine)
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Saber Features
Mixed Signal and Multiple domain simulator
Has a fully supported mixed signal hardware description language
Large library of models (~600). New models can be added through the
hardware description language. (I.e. motors, gears, cavitation, flexible lines,
A to D’s, D-flip flops, Z- domain rational polynomial, State Averaged Power
Supply models etc.)
Large Component Library (I.e. same as Spice plus fuses, motors, magnetic
cores, switches, A to D’s, PWM’s, Schmitt triggers, etc.)
Can run all spice models
Engineering units are maintain by the simulator
Can simulate signal flow diagrams and perform classical control analysis
Can co-simulate with VHDL and Verilog
Can extract any signal or variable in the simulation that was not specified
when the simulation was run
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Saber Features
No circuit/system size limitations as well no limitation on simulation
size
Piecewise linear algorithm yields superior convergence
Post Processing including a waveform calculator and over 55 build
in measurements I.e. rms, 3 db, Cpk, risetime, period, phase margin
Analysis types: AC, Large Signal AC, DC, transient, FFT, IFFT, pole
zero, Monte Carlo, Stress, Sensitivity, Distortion, two port, and Noise
Can link C and FORTRAN as well write functions in MAST
Can stop, change parameters and restart the simulator
Has a scripting language that controls the simulator, analysis and
post processing
182
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Level of Abstraction
Simulation Domain Coverage
Conceptual
Architectural
Saber
Behavioral
Control System
Simulators
Functional
Circuit Simulators (SPICE)
Device
Fab. Process
Physical
Analog
Nonelectrical
Digital
System
Technology
183
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RF/mwave
DSP
3-rd Party Tool Integration's for Saber
Through Mentor, Cadence and Viewlogic there are:
• IC Layout Tools
• Board Layout Tools
Thermal model generation through Sauna from Thermal Solutions
Solenoid Electro-Magnet characterization through Ansoft’s Maxwell
Interface to StateMate from I-Logics (Beta)
Customer developed optimizers
IC and Semiconductor characterization Tools
Co-Simulation with Verilog and VHDL
Data exchange with Matlab from The Mathworks
Data exchange with digitizing test equipment
184
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SPICE Applications
Electronic circuit simulation. Primary function is to optimize
electronic circuit configurations
Some versions can perform mixed signal simulations. Used for
mixed signal board and ASIC design
Can macro model other physical domains using the built in models
including some signal flow and controlled source models
Examples of Specific Applications:
Linear ASIC’s (Regulators, muliplexers, amplifiers, drivers etc.)
Linear board circuitry (Sensor interfaces, analog filters, PWM drives)
Has been used for thermal, mechanical, hydraulic etc. through
extensive macro modeling
185
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Saber Applications
General Purpose Non-Linear Ordinary Algebraic Differential
equation solver integrated with an event scheduler
Primary function is to optimize mixed signal and mixed physical
domain systems and circuits
Used for top down design methodology. System (Control system)
abstraction to hardware implementation.
Examples of Specific Applications:
Linear and Mixed signal ASIC’s (Regulators, Muliplexers, PWM’s,
Oscillators, etc.)
Linear and Mixed signal Boards (Sensor interface circuits, microprocessor (software algorithms), motor drivers, etc.)
186
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Saber Applications
Servo Mechanisms (Disk controllers, Satellite positioner, Throttle
Positioners etc.)
Electro-Hydraulic (Fuel Injection, Automotive Transmission
Controller, Sprayer Mechanisms)
Switching Power Supplies both full implementation and State
average (Buck, Boost, Cuk, Inverters etc.)
Mechatronic Systems (Doorlock Assemblies, Windshield wipers,
Sun Roof, Soft Start on a compressors etc.)
Sample Data System (Digital Filters, Data acquisition systems etc.)
187
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SPICE and Saber Algorithms
Both use Trapezoidal, Euler and Gear integration
algorithms
Saber has the Calaveras algorithm for handling mixed
mode and mixed signal simulations
Both have variable time step algorithms
188
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SPICE Algorithm
Newton-Raphson:
F(x)
error
(x0,F(x0),F’(x0))
(x1,F(x1),F’(x1))
(x2,F(x2),F’(x2))
x
(x3,F(x3),F’(x3))
Where F(x) =S x’s
F’(x) = d F(x)
dx
With Spice F(x) and F’(x) must be explicitly
known and coded into the simulator. Spice gives
an approximate solution to the exact problem.
189
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Saber Algorithm
Piecewise Linear Newton Raphson:
Fa(x)
(x0,Fa(x0))
(x3,Fa(x3))
(x1,Fa(x1))
x
(x2,Fa(x2))
Fa(x) is the piecewise linear approximation of F(x). All that is needed for this
solution is F(x). Saber gives the exact solution to an approximate problem.
Because the problem is made piecewise linear, there is a higher likelihood of
convergence.
190
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SPICE Macro Modeling
Can use the 20 to 30 primitive models and 10’s of 1000’s
of component models to create a model of a non existing
parts or functions
The resulting models will be in the electrical domain.
However the domain analogies can be employed. I.e
Current -> force or flow or torque and Voltage -> position
or velocity or mmf
Can employ equation based (controlled source) models
Can use signal flow block for modeling in some cases
191
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Saber Macro Modeling
Can use the approximately 600 primitive models and
10’s of 1000’s of component models to create a model of
a non existing part or function
Can create macro models in any domain
Can mix macro modeling with behavioral modeling in
MAST
192
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Macro Modeling
Example of Macro Modeling:
uA741 Macro-Model
Vcc
p
m
(-)
(+)
Vout
p
m
Vee
193
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Macro Modeling
Example of Macro Modeling:
Hydraulic Pressure Sensor
p Electrical
to
Control
mInterface
Supply Voltage
p1
Lag
Pressure Input
Pressurepres_out
to Var
Interface
Control p
to
Electrical
Interface m
H(s) = (s/w) +k 1
p2
194
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Sensor Output
Spice to Saber Conversions
All spice models can be converted into Saber models via
SPITOS (NSPITOS) - a conversion utility provided by
Analogy
NSPITOS handles Pspice, Hspice, Spice2 and Spice3
It has a GUI interface
Example to follow (conversion of LM6262)
195
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SPICE/Saber Conversion Example
Example of Spice to Saber Conversion:
Spice Model of a LM6262
*//////////////////////////////////////////////////////////////////////
* (C) National Semiconductor, Inc.
* Models developed and under copyright by:
* National Semiconductor, Inc.
*/////////////////////////////////////////////////////////////////////
* Legal Notice: This material is intended for free software support.
* The file may be copied, and distributed; however, reselling the
* material is illegal
*////////////////////////////////////////////////////////////////////
* For ordering or technical information on these models, contact:
* National Semiconductor's Customer Response Center
*
7:00 A.M.--7:00 P.M. U.S. Central Time
*
(800) 272-9959
* For Applications support, contact the Internet address:
* [email protected]
*//////////////////////////////////////////////////////////
*LM6262 High Speed OP-AMP MACRO-MODEL
*//////////////////////////////////////////////////////////
*
* connections:
non-inverting input
*
| inverting input
*
| | positive power supply
*
| | | negative power supply
*
| | | | output
*
| | | | |
*
| | | | |
.SUBCKT LM6262/NS 1 2 99 50 28
*
*Features:
*Low supply current = 5mA
*High bandwidth = 100MHz
*High slew rate = 300V/uS
*
****************INPUT STAGE**************
*
196
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SPICE/Saber Conversion Example
IOS 2 1 150N
*^Input offset current
CI1 1 0 2P
CI2 2 0 2P
R1 1 3 90K
R2 3 2 90K
I1 4 50 1M
R3 99 5 351.7
R4 99 6 351.7
Q1 5 2 45 QX
Q2 6 7 46 QX
R43 45 4 300
R44 46 4 300
*Fp2=230 MHz
C4 5 6 9.8376E-13
*
***********COMMON MODE EFFECT***********
*
I2 99 50 4M
*^Quiescent supply current
EOS 7 1 POLY(1) 16 49 3E-3 1
*Input offset voltage.^
R8 99 49 80K
R9 49 50 80K
*
*********OUTPUT VOLTAGE LIMITING********
V2 99 8 1.43
D1 9 8 DX
D2 10 9 DX
V3 10 50 2.23
*
**************SECOND STAGE**************
*
EH 99 98 99 49 1
F1 9 98 POLY(1) VA1 0 0 0 .85
G1 98 9 POLY(1) 5 6 0 6.5E-3 0 8.646E-3
*Fp1=17.935 KHz
R5 98 9 1MEG
C3 98 9 8.874P
*
***************POLE STAGE***************
*
*Fp=230 MHz
G3 98 15 9 49 1E-6
R12 98 15 1MEG
C5 98 15 6.9198E-16
*
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SPICE/Saber Conversion Example
***************POLE STAGE***************
*
*Fp=250 MHz
G5 98 18 15 49 1E-6
R15 98 18 1MEG
C6 98 18 6.3662E-16
*
*********COMMON-MODE ZERO STAGE*********
*
*Fpcm=10 KHz
G4 98 16 3 49 1E-8
L2 98 17 15.915E-3
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 50 99 POLY(1) V6 200U 1
VA1 99 93 0
E1 93 23 99 18 1
R16 24 23 10
D5 26 24 DX
V6 26 22 .63V
R17 23 25 10
D6 25 27 DX
C9 23 22 200P
V7 22 27 .63V
V5 22 21 .23V
D4 21 18 DX
V4 20 22 .23V
D3 18 20 DX
L3 22 28 100P
RL3 22 28 100K
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL QX NPN(BF=227.3)
*
.ENDS
198
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SPICE/Saber Conversion Example
Converted Saber Model of the LM6262
#//////////////////////////////////////////////////////////////////////
# (C) National Semiconductor,Inc.
# Models developed and under copyright by:
# National Semiconductor,Inc.
#
#/////////////////////////////////////////////////////////////////////
# Legal Notice: This material is intended for free software support.
# The file may be copied,and distributed
# material is illegal
#
#////////////////////////////////////////////////////////////////////
# For ordering or technical information on these models,contact:
# National Semiconductor's Customer Response Center
# 7:00 A.M.--7:00 P.M. U.S. Central Time
# (800) 272-9959
# For Applications support,contact the Internet address:
# [email protected]
#
#//////////////////////////////////////////////////////////
#LM6262 High Speed OP-AMP MACRO-MODEL
#//////////////////////////////////////////////////////////
#
# connections: non-inverting input
# | inverting input
# | | positive power supply
# | | | negative power supply
# | | | | output
#|||||
#|||||
template lm6262_sns 1 2 99 50 28
{
d..model dx = (is=1.00e-15)
spq..model qx = (type=_n,bf=2.27e+02)
#
#Features:
#Low supply current = 5mA
#High bandwidth = 100MHz
#High slew rate = 300V/uS
#
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SPICE/Saber Conversion Example
################INPUT STAGE##############
#
spi.os 2 1 = dc=150n
#^Input offset current
c.i1 1 0 = 2p
c.i2 2 0 = 2p
res.1 1 3 = 90k
res.2 3 2 = 90k
spi.1 4 50 = dc=1m
res.3 99 5 = 3.52e+02
res.4 99 6 = 3.52e+02
spq.1 5 2 45 0 = model=qx
spq.2 6 7 46 0 = model=qx
res.43 45 4 = 300
res.44 46 4 = 300
#Fp2=230 MHz
c.4 5 6 = 9.84e-13
#
###########COMMON MODE EFFECT###########
#
spi.2 99 50 = dc=4m
#^Quiescent supply current
spe1.os 7 1 16 49 = [3e-3,1]
#Input offset voltage.^
res.8 99 49 = 80k
res.9 49 50 = 80k
#
#########OUTPUT VOLTAGE LIMITING########
spv.2 99 8 = dc=1.43
d.1 9 8 = model=dx
d.2 10 9 = model=dx
spv.3 10 50 = dc=2.23
#
##############SECOND STAGE##############
#
spe.h 99 98 99 49 = 1
spf1.1 9 98 i(spv.a1) = [0,0,0,.85]
spg1.1 98 9 5 6 = [0,6.50e-03,0,8.65e-03]
#Fp1=17.935 KHz
res.5 98 9 = 1meg
c.3 98 9 = 8.874p
#
###############POLE STAGE###############
#
#Fp=230 MHz
spg.3 98 15 9 49 = 1e-6
res.12 98 15 = 1meg
c.5 98 15 = 6.92e-16
#
200
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Saber Simulation Controls (Reference)
The following slides give an overview of the simulation
controls available with Saber (the vast majority of these
do not typically need to be adjusted).
201
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Saber Simulator Controls
Saber has automatic algorithm stepping to aid in arriving
at a DC solution. They are:
•
•
•
•
No ramping
Gmin ramping
static ramping (source ramping)
dynamic ramping
There are 57 control parameters for these algorithms
There are a large number of control parameters for
transient analysis
202
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DC Simulation Controls
Parameter
algstart
debug
holdnodes
relholdnodes
Default
NO_Ramp
No
undefined
Yes
Notes
Specifies the initial algorithm of the pre-defined sequence to start with or
the single algorithm to be used for the analysis
Display debug information during analysis
List nodes that are to be held at specific values during the operating point
analysis
Controls the release of the holdnodes during final solution of operating
point
Specifies amount of information to display while the simulator if doing
computations
monitor
0
density
1
Specifies the density of the sample points
nsdensity
1
Specifies a global newton step factor
fniter
100
Specifies the maximum number of Newton-Raphson iterations.
203
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Mixed-signal Simulation Controls
Parameter
Default
Notes
tresolution
1p
Specifies the time resolution for
the discrete time simulation.
aditer
3
Specifies the maximum number
of analogy/digital iterations.
eviter
5000
Specifies maximum number of
event iterations in a mixed-mode
analysis.
204
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Dynamic Ramping Controls
Parameter
Default
Notes
dr_tstep
10n
Specifies the time step for dynamic ramping
dr_trise
200n
Specifies the ramp rise time for dynamic ramping.
dr_tsettle
200u
Specifies the settling time for dynamic ramping
dr_order
2
Specifies the order of the Gear integration method
used in dynamic ramping
dr_terror
0.05
dr_terrnorm
dynamic
Specifies the truncation error for the dynamic
ramping.
Specifies the type of norm used for dynamic ramping
truncation error calculations.
dr_tniter
10
Specifies the number Newton Raphson iterations at
each time step in dynamic ramping
dr_samestep
1
dr_stepsize
variable
Specifies how many steps are taken of a given
stepsize before a longer stepsize is used for dynamic
ramping.
Specifies the stepsize control for dynamic ramping as
Fixed or Variable
dr_tsmin
1f
Specifies the minimum time step used for dynamic
ramping.
dr_tsmax
0.1
Specifies the maximum time step used for dynamic
ramping.
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GMIN Ramping
Parameter
Default Notes
gramping
No
Specifies if GMIN algorithm will be used exclusively
gbegin
1
Specifies the starting value for gmin ramping
gstep
1000
Specifies the logarithmic step value (divisor) for gmin
ramping
gend
1p
Final value of conductance for gmin ramping.
gmiter
10
Specifies the maximum number of Newton-Raphson
iterations for each gmin ramping iteration
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Static Ramping
Parameter
Default
SR_SStep
0.001
SR_ORDer
SR_TERror
SR_TERRType
2
0.005
STATIC
SR_TNiter
SR_SAMEStep
SR_STEPsize
SR_SSMIN
SR_SSMAX
6
1
VARiable
100p
10000
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Transient Analysis Controls
Parameter
Default
Notes
tend
required
Specifies the end time for the simulation.
tstep
required
Specifies the step size of the first time step and it, by default
controls the time steps during the simulation. 10-5 ts < h < 107 ts
tbegin
undefined
Specifies the begin time of the simulation. If undefined the simulation
starts with the values in the IP file. If specified it shifts the values in
the IP file by the specified value
terror
0.005
Specifies the value which the LTE is compared to. (See slide 26)
terrtype
dynamic
terrnorm
6
Specifies how the truncation error is calculated. Dynamic uses the
elements which have derivatives. Static uses non derivative
elements. All uses both types.
Specifies how the LTE is calculated for comparison to terror. See
SaberBook
density
1
Specifies the multiplier which increases the number of sample
points. (See slide 19)
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Transient Analysis Controls
Parameter
Default
Notes
tresolution
1p
Specifies the time resolution for discrete time simulation.
aditer
3
Specifies the number of analog/digital iterations for mixed signal
simulations.
zditer
100
Specifies the maximum number of Newton-Raphson iterations used
at a scheduled time step.
stepsize
variable
Determines how the step size (h) is determined. Fixed will caused
fixed time steps to be taken (h=ts) and no LTE checking will
performed. Variable will cause h to be calculated.
samestep
1
Defines the number of same size time steps (h) when the variable
time step is employed.
tsmax
undefined
tsmin
undefined
If specified it determines the upper limit for h for the variable time
step algorithim.
If specified it determines the lower limit for h for the variable time
step algorithim.
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Transient Analysis Controls
Parameter
Default
Notes
order
2
Order of the Gear algorithm
method
gear
Can select either Gear 1, Gear 2 and Trapezoidal
algorithm
NewtonRaphson
tniter
3
Selects the iteration algorithm. Newton-Raphson should be used on
99% of the circuit. There is a small class of the circuits where the
other algorithm (Katzenelson) will converge and Newton-Raphson
will not.
Maximum number of Newton-Raphson iterations at each time step.
fniter
100
Maximum number of iterations of the Newton-Raphson algorithm
when it is selected.
fkiter
50
nsdenity
1
nslimit
yes
Maximum number of Katzenelson iterations when that algorithm is
selected.
Specifies the number Newton Step points relative to the amount
specified in templates of the circuit.
Specifies whether Newton step will be limited at each time point.
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Technology-Specific Labs
In this part of the class, we will focus on more
complicated designs and simulation exercises.
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SaberDesigner Menus Summary
SaberDesigner Menu Summary
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SaberSketch Pulldown Menu Bar
File/Design
Sketch Window
Schematic/Symbol
Control
Control
Control
Edit/Preferences
Design Control
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SaberSketch Pulldown Menu Bar
Alternate Simulation
Scope/Report
Alternate Tool Bar
Analyses Control
Control
Icon Control
Extract Simulation/
Schematic Probe SaberSketch Window
Plot File Data
Control
Control
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SaberSketch Icon Bar
New Window Save Window Cut to Clipboard
Open a file
Print Window
Copy to Clipboard
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Paste
Zoom In
Zoom Out
Zoom to Fit
SaberSketch Icon Bar
Cascade
Windows
Toggle Grid
Tile Windows
Create Bundle
Create Wire
Show/Hide SaberGuide
Waveform Probe
Icon Bar
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Property Editor
SaberSketch Tool Bar
AIM Command Line
Parts Gallery
Drawing Tool
Macro Recorder
Design Tool
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Testify
Report Tool
SaberGuide Icon Bar
Operating Point
Analysis
DC Transfer
Analysis
AC Analysis
Operating Point/
Transient Analysis
Pole-Zero
Transient Analysis
Analysis
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SaberGuide Icon Bar
Experiment
Interrupt Simulation
Sensitivity
Analysis
Monte Carlo
List/Alter
Update Probes
Analysis
Parameter Sweep
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SaberScope Pulldown Menu Bar
Graph/Plot
Graph Window
SaberScope
File Control
Control
Window Control
Alternate Tool Bar
Edit/Preferences
Icon Control
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SaberScope Icon Bar
Create graph
Window
Clear graph
Create Bus
Toggle Grid
At X Meas.
Burst Bus
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Cross Probe
At Y Meas.
CD-ROM Development/Analysis
CD-ROM Development/Analysis
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Control System Analysis
S
G1 (s)
G2 (s)
M&L(s)
motor & load
H(s)
The goal of the next lab is to show how SaberDesigner can be used to design a
system to control the speed of a D.C. motor in a CD-ROM. To do this, you’ll follow
some basic steps and pick up some skills in SaberDesigner.
Basic Design Steps
•
•
•
•
Determine an acceptable value for loop gain
Determine phase margin without compensation
Insert G2(s) (compensation block)
Evaluate and ensure loop stability
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Schematic for Lab
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Accuracy & Stability
This circuit is a closed-loop control system. In closed-loop
control systems, two criteria typically define the system
performance: accuracy and stability.
Accuracy: The accuracy of a control system specifies how
closely the actual behavior of the thing that is to be controlled
(often referred to as the “plant”), actually matches the desired
behavior.
Stability: To guarantee stability, we want to make sure that the
system does not have both positive feedback and gain at any
frequency.
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CD-ROM Specifications
For the CD ROM Controller:
Accuracy: error <= 2%
Stability: phase margin >= 40 degrees
In the next few pages you will determine whether the circuit
can meet the above-noted constant-input accuracy
specification. To do this, you’ll evaluate the operating point.
As long as the error signal is less than 2% of the input signal,
you are within a 2% accuracy specification.
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Lab #12 - Accuracy and Stability
In this lab, you will ensure both the accuracy and stability
of the CD-ROM control loop.
Perform the steps beginning on the page titled Lab #12
in your exercise manual.
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Lab #12 - Review
Increased the system gain to meet the accuracy specification.
Opened the feedback loop from inside of Saber using the powerful List/Alter
feature.
Performed a Small Signal AC Analysis.
Performed automatic phase margin measurements in SaberScope.
Used pole/zero analysis to get a clear understanding of why there was a
stability problem.
Modified the design (added a lead-lag compensator) with the SaberSketch
schematic capture tool.
Used the waveform calculator to verify the transfer function of the
compensator, without additional schematic work and without re-running the
simulation.
Used loop analysis and tweaked the parameters of the compensator to meet the
system design requirements (adequate phase margin).
Reiterated the process to verify that the design changes were adequate.
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Uncompensated System PZ
Less stable with > gain
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Schematic with Compensator
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Tune the Compensator
In this case, you used SaberDesigner as a design aid to
determine optimum compensator settings.
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Compensated System PZ
More stable with > gain
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Schematic Capture
Schematic Capture with SaberSketch
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Levels of Abstraction
Control
Input
+
Difference
Compensation
Driver
-
Feedback
PWM
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Plant
Component-level Driver Stage
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Lab #13 - Capture Driver
In this lab, you will use SaberSketch to schematically
capture the component level driver for the CD-ROM
controller.
Perform the steps beginning on the page titled Lab #13
in your exercise manual.
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Lab #13 - Review
In this lab exercise, you did the following:
Built up a circuit from scratch
Used the Parts Gallery and Saber Parts Libraries
Added, connected, and parameterized components
Became more familiar with schematic capture using
SaberSketch
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DC Transfer Analysis (Optional)
Overview
Test and evaluate component-level driver stage (does it meet spec?).
DC Transfer Analysis
The SaberGuide Transcript window
Run command script
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Specifications for Driver Circuit
S p e c ific a t io n s fo r Mo t o r D riv e r Circ u it
Output Voltage Range:
-12 to +12 Volts for a minimum input
signal of -2V to +2V
(Output is in phase with the input)
(e.g. input rise causes output to rise)
Output Current Source (peak):
400mA
Output Current Sink (peak):
Input Impedance:
400mA
25 k-ohm, minimum
Output Voltage Rise time (10% - 90%):
500ns, Maximum
Output Voltage Fall time (10% - 90%):
500ns, Maximum
Propagation Delay, Input to Output:
1us, Maximum
Nominal Supply voltages:
+15 Volts (+/- 10%)
-15 Volts (+/- 10%)
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Test Conditions for Driver Circuit
Test condit ions:
Supply Voltage
Nominal +/- 1%
Temperature
25 Degrees C
Load
47 ohm resistor, 10 Watt
Input Signal
Square wave:
period:
1ms (1kHz)
Duty cycle:
50% +/- 1%
Amplitude:
+/- 13 Volts (peak to peak)
Rise time:
1 us
Fall time :
1us
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Preparation for Lab #14
The first specification states:
What the output does as a function of the input neglecting
switching times and storage effects
What input values are necessary to ensure that the driver stage
is properly saturated
The first bullet points toward DC analysis. The second bullet
points toward varying the input as a part of the analysis
This is accomplished by executing a DC Transfer Analysis (it
can also be done by running a DC analysis within a vary loop)
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Lab #14 - DC Transfer Analysis
In this lab, you will analyze the voltage input to voltage
output transfer function of the driver circuit. This will
allow you to verify that it can work over the range of
operation mandated by the specification.
Perform the steps beginning on the page titled Lab #14
in your exercise manual.
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Lab #14 - Review
In this lab you:
Investigated the integrity of the circuit
• Does the circuit operate as intended?
Evaluated input/output DC transfer function
• Varied the input source for DC Transfer Analysis
Performed a Parametric Component Search
Saw some other aspects of SaberDesigner
SaberGuide Transcript window
Netlist Re-Load
Troubleshooting with SaberScope and the waveform calculator
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General Overview
So far, in the CD-ROM System:
Introduction to SaberDesigner
Design on the top level
Design on the circuit level
DC Transfer Analysis
• Meet accuracy and stability specs?
• Schematic capture
• Meet transfer function specs?
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Characterize Switch Driver
In the next lab:
Top-down design and simulation
Bottom-up characterization
Mixed technology
• Ensure accurate high-level models through component-level measurements
• Transient (time-domain) analysis
• Electromechanical load
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Top Down Design
Top-down design is a key technology for developing large
systems.
Handle complexity
• design
• specifications
• management
Early detection and correction of design-flaws
Resilient system definition
• If part of system needs to be redesigned, the effects on the rest of the system
are limited and understood.
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Top Down Design & Saber
The Saber simulator is a key technology for top-down design.
• Test the design specifications themselves
• Test at each level of design before “sclerosis” sets in
• Test concepts (e.g. topology) without worrying about implementation
• If the topology doesn’t work or is sub-optimal, implementation details won’t help
• Simulate on all these levels simultaneously in the same simulator.
• Only have to learn one set of tools
• Don’t have to worry about conflicting data bases
• Simulate various portions of the system at various levels of abstraction
simultaneously.
• Share designs across
• different disciplines
• different organizations
• design team hierarchy
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Designing on Different Levels - Top
Control
Input
Difference
Driver
Compensation
Plant
Feedback
On the top level of the CD-ROM motor controller, issues
relate to loop dynamics.
• rate-error
• stability
Advantages:
• Faster simulations
• Parameters appropriate to this level
• Switching times
• Impedances
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Designing on Different Levels - Bottom
On the component level, issues relate to the components
themselves.
• regions of operation
• tolerances
• judicious component selection
Disadvantages:
• Slower simulation times
• Tougher to write models
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Bottom-Up Characterization
By measuring the characteristics of the component-level stage, you can
have the accuracy you need for such a test, with considerable simulation
speed improvements.
The following lab will show this by characterizing the component-level
driver stage to a switch-level.
PWM
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Driver Stage Characterization
There are several ways to characterize the driver stage. The
first question you need to answer is “what is it I am trying to
do?”
• Have parameters appropriate to the specification of this stage
• Output impedance modeled
• Timing
• Power supply effects
• Input impedance is neglected - we’ll be driving it digitally
• Have fast simulations
Toward this end, you have several options to choose from for
the models themselves:
• sw_l4
• bjt_l4
• write your own model
• from scratch in MAST
• MAST is covered in the Introductory Modeling Class using MAST and Advanced
Saber/MAST training courses.
• macro-model
• combination macro-model, MAST (and graphical modeling)
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Analog Switch with Digital Control
Digitally controlled analog switch
Implemented as a time-varying resistance
in
r
time
Advantages
• Much faster than fully analog
•
•
• Does not include delay
• Does not include base current
• Only models saturation (Vsat=0)
transistor
Simple to characterize
Includes Ron, Roff, trise, tfall
and cutoff
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Disadvantages
sw_l4 Characterization
• “Resistance”
• on
• off
• Transition times
• on off
• off on
• Delay times
• on off
• off on
• Digital buffer and inverter will model switching delay
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How to Measure Parameters
To measure timing parameters:
To measure resistance parameters:
• generate data with transient analysis
• measure parameters with SaberScope
• DC quantity
• could generate data with DC Vary
• data available from transient analysis - measure in SaberScope
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Overview
To facilitate design:
• Use models with appropriate parameters for each stage of design.
To get faster simulations:
• Use higher-level models
• Use digital models where possible
To get accurate models:
• Bottom-up characterization
In this lab:
•
•
•
•
Characterize component-level driver to switch-level model
Evaluate switch-level model
Replace specification load (47 Ohm resistor) with motor and CD disc
As well, keep track of simulation times to evaluate speed improvements.
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Lab #15 - Switch Driver
In this lab, you will replace the component-level driver
with an accurate, characterized switch-level driver in the
CD-ROM system. This will allow for faster, simpler - yet
accurate simulation results.
Perform the steps beginning on the page titled Lab #15
in your exercise manual.
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Lab # 15 - Review
Simulation Speed: Analog vs. Mixed Mode
The simulation for the switch-level simulation was much faster than that for
the component-level simulation. Reasons for this include:
The circuit itself is simpler - fewer nodes for the Saber simulator to solve.
Portions of the behavior of the circuit are modeled digitally. As a rule, digital
models simulate faster than analog models.
The simulator does not need to take as many time-steps.
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Review - Timesteps for Drivers
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Add a Motor Load
Overview
• We have seen from the previous comparison that the switch-level model is an
appropriate representation of the drive stage for this application—with
considerable simulation speed improvement.
• The driver stage meets the specifications, but will it work when we put it in the
system?
• Let’s go beyond the specifications by testing it with the load that it will actually
be driving.
• In the next section, you will go back to the schematic and replace the resistive
load (from the specifications) with the motor and its load and evaluate the
circuit’s performance.
• (To avoid over-writing our “known-good” copy, your first step in SaberSketch
will be to copy this schematic to a new file which you will then manipulate.)
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Lab #16 - Add motor Load
In this lab, you will verify the system can drive an actual
motor load, rather than a resistive load.
Perform the steps beginning on the page titled Lab #16
in your exercise manual.
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Lab #16 - Review
In this lab, you:
Replaced specification load (47W) with motor and CD disc
Discovered problem (inductive kick) not anticipated by
specifications
Corrected problem in circuitry
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CD-ROM So Far
Introduction to SaberDesigner
Design on the top level
• Ensure accuracy and stability
Design on the circuit level
• Schematic capture
Top-down design and simulation
Bottom-up characterization
• Ensure accurate high-level models through component-level
measurements
• Transient (time-domain) analysis
Mixed technology
• Electromechanical load
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CD-ROM This Section
Tying it all together: Characterized switch-level driver at the
system level.
Hierarchical design
Hierarchical symbol generation
Mixed Electrical and Control system simulation
Cross-Probing
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Complete CD-ROM System
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Compensation Block
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PWM/SWITCH Combination
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Simple PWM
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PWM Waveforms
Input Signal
S um mer and Com par at or
Out put Signal
Input Signal
Modula t ion Signa l
(high fr equen cy)
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Output Driver (Characterized)
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Lab #17 - Complete CD-ROM Design
In this lab, you will complete the CD-ROM analysis. You
will use hierarchical design techniques to develop the
system.
Perform the steps beginning on the page titled Lab #17
in your exercise manual.
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CD-ROM Labs - Review/Summary
Summary
You have now used many of the standard analysis tools that
are part of SaberDesigner. You have, among other things,
accomplished the following:
Analyzed several portions of a CD-ROM controller and changed the design
because of inadequate phase margin.
Created schematics using SaberSketch.
Characterized a fast-simulating switch-based driver from data you measured
with SaberDesigner.
Tested this switch-based driver with a mechanical load (motor).
Made design improvements based on this analysis.
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Review/Summary - Continued
Performed multiple types of analysis, including:
DC Operating Point Analysis
AC (Small signal frequency-domain) Analysis
DC Transfer Analysis
Transient (Time-domain) Analysis
You then again performed mixed-technology simulations: this time a
mix of control system models and electrical-based models were used.
You introduced several levels of hierarchy to help gain a conceptual
systems view of the controller.
You used SaberSketch to create symbols to aid in hierarchical design
development.
You explored sophisticated probing techniques allowing you a variety
of methods for analyzing simulation results.
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Congratulations!
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